alc5505_coef_set
alc5505_coef_set(codec, 0x3000, 0x000c); /* DSP CPU stop */
alc5505_coef_set(codec, 0x880c, 0x0008); /* DDR enter self refresh */
alc5505_coef_set(codec, 0x61c0, 0x11110080); /* Clock control for PLL and CPU */
alc5505_coef_set(codec, 0x6230, 0xfc0d4011); /* Disable Input OP */
alc5505_coef_set(codec, 0x61b4, 0x040a2b03); /* Stop PLL2 */
alc5505_coef_set(codec, 0x61b0, 0x00005b17); /* Stop PLL1 */
alc5505_coef_set(codec, 0x61b8, 0x04133303); /* Stop PLL3 */
alc5505_coef_set(codec, 0x6220, (val | 0x3000)); /* switch Ringbuffer clock to DBUS clock */
alc5505_coef_set(codec, 0x61b8, 0x04133302);
alc5505_coef_set(codec, 0x61b0, 0x00005b16);
alc5505_coef_set(codec, 0x61b4, 0x040a2b02);
alc5505_coef_set(codec, 0x6230, 0xf80d4011);
alc5505_coef_set(codec, 0x6220, 0x2002010f);
alc5505_coef_set(codec, 0x880c, 0x00000004);
alc5505_coef_set(codec, 0x61b0, 0x5b14); /* PLL1 control */
alc5505_coef_set(codec, 0x61b0, 0x5b16);
alc5505_coef_set(codec, 0x61b4, 0x04132b00); /* PLL2 control */
alc5505_coef_set(codec, 0x61b4, 0x04132b02);
alc5505_coef_set(codec, 0x61b8, 0x041f3300); /* PLL3 control*/
alc5505_coef_set(codec, 0x61b8, 0x041f3302);
alc5505_coef_set(codec, 0x61b8, 0x041b3302);
alc5505_coef_set(codec, 0x61b8, 0x04173302);
alc5505_coef_set(codec, 0x61b8, 0x04163302);
alc5505_coef_set(codec, 0x8800, 0x348b328b); /* DRAM control */
alc5505_coef_set(codec, 0x8808, 0x00020022); /* DRAM control */
alc5505_coef_set(codec, 0x8818, 0x00000400); /* DRAM control */
alc5505_coef_set(codec, 0x6220, 0x2002010f); /* I/O PAD Configuration */
alc5505_coef_set(codec, 0x6220, 0x6002018f);
alc5505_coef_set(codec, 0x61ac, 0x055525f0); /**/
alc5505_coef_set(codec, 0x61c0, 0x12230080); /* Clock control */
alc5505_coef_set(codec, 0x61b4, 0x040e2b02); /* PLL2 control */
alc5505_coef_set(codec, 0x61bc, 0x010234f8); /* OSC Control */
alc5505_coef_set(codec, 0x880c, 0x00000004); /* DRAM Function control */
alc5505_coef_set(codec, 0x880c, 0x00000003);
alc5505_coef_set(codec, 0x880c, 0x00000010);