adv7511_rd
ed.segment = adv7511_rd(sd, 0xc4);
u8 status = adv7511_rd(sd, 0x42);
u8 edidRdy = adv7511_rd(sd, 0xc5);
int segment = adv7511_rd(sd, 0xc4);
state->chip_revision = adv7511_rd(sd, 0x0);
chip_id[0] = adv7511_rd(sd, 0xf5);
chip_id[1] = adv7511_rd(sd, 0xf6);
adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask);
return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT;
return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT;
reg->val = adv7511_rd(sd, reg->reg & 0xff);
if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) {
buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i);
(adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no",
(adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no",
(adv7511_rd(sd, 0xaf) & 0x02) ?
(adv7511_rd(sd, 0xa1) & 0x3c) ?
states[adv7511_rd(sd, 0xc8) & 0xf],
errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter,
adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96));
v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full");
if (adv7511_rd(sd, 0xaf) & 0x02) {
u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80;
u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 |
adv7511_rd(sd, 0x02) << 8 |
adv7511_rd(sd, 0x03);
u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2;
u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f;
CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 |
adv7511_rd(sd, 0x08) << 8 |
adv7511_rd(sd, 0x09);
CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 |
adv7511_rd(sd, 0x05) << 8 |
adv7511_rd(sd, 0x06);
if ((adv7511_rd(sd, 0x41) & 0x40) == 0)
irqs_rd = adv7511_rd(sd, 0x94);
irq_status = adv7511_rd(sd, 0x96);
cec_irq = adv7511_rd(sd, 0x97);