alx_write_phy_reg
alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN);
alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0);
if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) ||
alx_write_phy_reg(hw, MII_CTRL1000, giga) ||
alx_write_phy_reg(hw, MII_BMCR, cr))
err = alx_write_phy_reg(hw, MII_BMCR, cr);
alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED);
int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
return alx_write_phy_reg(hw, addr, val);