drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

403

s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

104

uint32_t alpha_mode = 2;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

110

alpha_mode = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

115

alpha_mode = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

132

BLND_ALPHA_MODE, alpha_mode,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2908

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2911

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2915

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

546

s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

176

s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2937

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2940

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2944

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

449

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

451

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

195

s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3793

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3796

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3800

blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

145

enum mpcc_alpha_blend_mode alpha_mode;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

338

uint32_t alpha_mode;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

453

MPCC_ALPHA_BLND_MODE, &s->alpha_mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

85

MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

554

MPCC_ALPHA_BLND_MODE, &s->alpha_mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

58

MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1483

MPCC_ALPHA_BLND_MODE, &s->alpha_mode,

drivers/gpu/drm/logicvc/logicvc_layer.c

191

if (layer->config.alpha_mode == LOGICVC_LAYER_ALPHA_LAYER) {

drivers/gpu/drm/logicvc/logicvc_layer.c

358

alpha = (layer->config.alpha_mode == LOGICVC_LAYER_ALPHA_PIXEL);

drivers/gpu/drm/logicvc/logicvc_layer.c

407

&config->alpha_mode);

drivers/gpu/drm/logicvc/logicvc_layer.c

537

if (layer->config.alpha_mode == LOGICVC_LAYER_ALPHA_LAYER)

drivers/gpu/drm/logicvc/logicvc_layer.h

29

u32 alpha_mode;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1061

VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);

drivers/gpu/drm/rockchip/rockchip_drm_vop.h

206

struct vop_reg alpha_mode;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1840

alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1843

alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1850

alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1855

alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

27

u32 alpha_mode:1;

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

1216

.alpha_mode = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 1),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

130

.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

148

.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

218

.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

320

.alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

337

.alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

354

.alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

419

.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

438

.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

453

.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

544

.alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18),

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

561

.alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19),

drivers/media/pci/ivtv/ivtv-ioctl.c

1539

static const char * const alpha_mode[4] = {

drivers/media/pci/ivtv/ivtv-ioctl.c

1574

alpha_mode[(data[0] >> 1) & 0x3],

drivers/video/fbdev/au1200fb.c

116

unsigned int alpha_mode;

drivers/video/fbdev/au1200fb.c

1313

val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN);

drivers/video/fbdev/au1200fb.c

1399

pdata->alpha_mode = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_AEN) >> 1;