adau1372
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
adau1372->clock_provider = true;
adau1372->clock_provider = false;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
slot_width = adau1372->slot_width;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
adau1372->slot_width = 0;
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
if (adau1372->clock_provider)
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;
adau1372->slot_width = width;
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);
regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);
struct adau1372 *adau1372 = snd_soc_dai_get_drvdata(dai);
&adau1372->rate_constraints);
static int adau1372_enable_pll(struct adau1372 *adau1372)
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);
dev_err(adau1372->dev, "Failed to lock PLL\n");
static int adau1372_set_power(struct adau1372 *adau1372, bool enable)
if (adau1372->enabled == enable)
ret = clk_prepare_enable(adau1372->mclk);
if (adau1372->pd_gpio)
gpiod_set_value(adau1372->pd_gpio, 0);
if (adau1372->switch_mode)
adau1372->switch_mode(adau1372->dev);
regcache_cache_only(adau1372->regmap, false);
if (adau1372->use_pll) {
ret = adau1372_enable_pll(adau1372);
if (!adau1372->pd_gpio)
regmap_update_bits(adau1372->regmap,
regcache_cache_only(adau1372->regmap, true);
if (adau1372->pd_gpio)
gpiod_set_value(adau1372->pd_gpio, 1);
clk_disable_unprepare(adau1372->mclk);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
regcache_sync(adau1372->regmap);
if (adau1372->pd_gpio) {
gpiod_set_value(adau1372->pd_gpio, 1);
regcache_mark_dirty(adau1372->regmap);
regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,
clk_disable_unprepare(adau1372->mclk);
regcache_cache_only(adau1372->regmap, true);
adau1372->enabled = enable;
struct adau1372 *adau1372 = snd_soc_component_get_drvdata(component);
return adau1372_set_power(adau1372, true);
return adau1372_set_power(adau1372, false);
static int adau1372_setup_pll(struct adau1372 *adau1372, unsigned int rate)
regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);
struct adau1372 *adau1372;
adau1372 = devm_kzalloc(dev, sizeof(*adau1372), GFP_KERNEL);
if (!adau1372)
adau1372->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(adau1372->mclk))
return PTR_ERR(adau1372->mclk);
adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
if (IS_ERR(adau1372->pd_gpio))
return PTR_ERR(adau1372->pd_gpio);
adau1372->regmap = regmap;
adau1372->switch_mode = switch_mode;
adau1372->dev = dev;
adau1372->rate_constraints.list = adau1372_rates;
adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);
adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;
dev_set_drvdata(dev, adau1372);
rate = clk_get_rate(adau1372->mclk);
ret = adau1372_setup_pll(adau1372, rate);
adau1372->use_pll = true;