BXT_PORT_PLL_ENABLE
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
BXT_PORT_PLL_ENABLE(port),
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
BXT_PORT_PLL_ENABLE(port),
val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A));
MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B));
MMIO_D(BXT_PORT_PLL_ENABLE(PORT_C));