ag71xx_wr
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1);
ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);
ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);
ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);