acp_writel
acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
acp_writel(adata->tdm_fmt, rtd->acp5x_base + frmt_reg);
acp_writel(val, rtd->acp5x_base + reg_val);
acp_writel(period_bytes, rtd->acp5x_base + water_val);
acp_writel(buf_size, rtd->acp5x_base + buf_reg);
acp_writel(val, rtd->acp5x_base + reg_val);
acp_writel(1, rtd->acp5x_base + ier_val);
acp_writel(val, rtd->acp5x_base + reg_val);
acp_writel(0, rtd->acp5x_base + ACP_HSTDM_IER);
acp_writel(0, rtd->acp5x_base + ACP_I2STDM_IER);
acp_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp5x_base +
acp_writel(PAGE_SIZE_4K_ENABLE, rtd->acp5x_base +
acp_writel(low, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val);
acp_writel(high, rtd->acp5x_base + ACP_SCRATCH_REG_0 + val + 4);
acp_writel(I2S_HS_TX_MEM_WINDOW_START,
acp_writel(I2S_SP_TX_MEM_WINDOW_START,
acp_writel(I2S_HS_RX_MEM_WINDOW_START,
acp_writel(I2S_SP_RX_MEM_WINDOW_START,
acp_writel(DMA_SIZE, rtd->acp5x_base + reg_dma_size);
acp_writel(acp_fifo_addr, rtd->acp5x_base + reg_fifo_addr);
acp_writel(FIFO_SIZE, rtd->acp5x_base + reg_fifo_size);
acp_writel(BIT(I2S_RX_THRESHOLD) | BIT(HS_RX_THRESHOLD)
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_HSTDM_ITER);
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_TXFRMT);
acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_ITER);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_I2STDM_ITER);
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_TXFRMT);
acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_ITER);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_HSTDM_IRER);
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_HSTDM_RXFRMT);
acp_writel(val | 0x2, adata->acp5x_base + ACP_HSTDM_IRER);
acp_writel((rtd->xfer_resolution << 3), rtd->acp5x_base + ACP_I2STDM_IRER);
acp_writel(adata->tdm_fmt, adata->acp5x_base + ACP_I2STDM_RXFRMT);
acp_writel(val | 0x2, adata->acp5x_base + ACP_I2STDM_IRER);
acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
acp_writel(0, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
acp_writel(1, adata->acp5x_base + ACP_EXTERNAL_INTR_ENB);
acp_writel(BIT(HS_TX_THRESHOLD), vg_i2s_data->acp5x_base +
acp_writel(BIT(I2S_TX_THRESHOLD),
acp_writel(BIT(HS_RX_THRESHOLD), vg_i2s_data->acp5x_base +
acp_writel(BIT(I2S_RX_THRESHOLD),
acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
acp_writel(0x03, acp5x_base + ACP_CLKMUX_SEL);
acp_writel(0x00, acp5x_base + ACP_CLKMUX_SEL);
acp_writel(0x00, acp5x_base + ACP_CONTROL);
acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
acp_writel(1, acp5x_base + ACP_SOFT_RESET);
acp_writel(0, acp5x_base + ACP_SOFT_RESET);
acp_writel(0x01, acp5x_base + ACP_EXTERNAL_INTR_ENB);
acp_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp5x_base +
acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_CNTL);
acp_writel(0x00, acp5x_base + ACP_EXTERNAL_INTR_ENB);
acp_writel(0x01, acp5x_base + ACP_CONTROL);