add_1reg
EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32);
EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32);
EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32);
EMIT2(0xF7, add_1reg(0xD8, dst_reg));
EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
EMIT2(0xF7, add_1reg(0xF0, src_reg));
EMIT2(0xF7, add_1reg(0xF8, src_reg));
EMIT2(0xD1, add_1reg(b3, dst_reg));
EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
EMIT2(0xD3, add_1reg(b3, dst_reg));
EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
EMIT1(add_1reg(0xC8, dst_reg));
add_1reg(0xC8, dst_reg));
EMIT2(add_1reg(0x40, dst_reg), insn->off);
EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val);
EMIT3(0xC1, add_1reg(0xF8, dreg_hi), value);
EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
EMIT2(0xF7, add_1reg(0xE0, src_lo));
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_hi));
EMIT2(0xF7, add_1reg(0xE0, src_hi));
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
EMIT2(0xF7, add_1reg(0xE0, src_lo));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi));
EMIT2(0xF7, add_1reg(0xE0, dst_hi));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
EMIT2(0xF7, add_1reg(0xE0, dst_lo));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
EMIT2(0xF7, add_1reg(0xE0, dst_lo));
EMIT3(0x83, add_1reg(0xE8, IA32_EBP), SCRATCH_SIZE + 12);
EMIT3(0x83, add_1reg(0xC0, IA32_EBP), SCRATCH_SIZE + 12);
EMIT3(0x83, add_1reg(0xF8, IA32_EBX), hi);
EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo);
EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 0x01);
EMIT3(0x83, add_1reg(0xD0, IA32_EBX), 0x00);
EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE);
EMIT3(0x83, add_1reg(0xC0, IA32_ESP), bytes_in_stack);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2(add_1reg(0x40, IA32_EAX), insn->off);
EMIT1_off32(add_1reg(0x80, IA32_EAX),
EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
EMIT3(0x83, add_1reg(0xC0, IA32_ESP), 32);
EMIT3_off32(0xC7, add_1reg(0x40, IA32_EBP),
EMIT2_off32(0xC7, add_1reg(0xC0, dst),
EMIT2_off32(0xC7, add_1reg(0xC0, sreg_lo), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, sreg_hi), hi);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
EMIT2(0xF7, add_1reg(0xE0, sreg));
EMIT3(0xC1, add_1reg(0xC8, dreg_lo), 8);
EMIT1(add_1reg(0xC8, dreg_lo));
EMIT1(add_1reg(0xC8, dreg_lo));
EMIT1(add_1reg(0xC8, dreg_hi));
EMIT2(0xF7, add_1reg(0xF0, IA32_ECX));
EMIT2(0xD3, add_1reg(b2, dreg));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);
EMIT3(0x83, add_1reg(0xD0, dreg), val);
EMIT3(0x83, add_1reg(0xC0, dreg), val);
EMIT3(0x83, add_1reg(0xD8, dreg), val);
EMIT3(0x83, add_1reg(0xE8, dreg), val);
EMIT3(0x83, add_1reg(0xC8, dreg), val);
EMIT3(0x83, add_1reg(0xE0, dreg), val);
EMIT3(0x83, add_1reg(0xF0, dreg), val);
EMIT2(0xF7, add_1reg(0xD8, dreg));
EMIT2(0xF7, add_1reg(0xD8, dreg_lo));
EMIT3(0x83, add_1reg(0xD0, dreg_hi), 0x00);
EMIT2(0xF7, add_1reg(0xD8, dreg_hi));
EMIT2(0xD3, add_1reg(0xE0, dreg_lo));
EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
EMIT3(0xC1, add_1reg(0xE0, dreg_lo), val);
EMIT3(0xC1, add_1reg(0xE0, dreg_lo), value);
EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val);
EMIT3(0xC1, add_1reg(0xE8, dreg_hi), value);