drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1085

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1086

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1123

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1124

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1132

gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1134

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1195

static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1197

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1199

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1218

a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

123

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1239

fuse_val = a6xx_cx_misc_read(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

124

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1255

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1256

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1279

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1280

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1304

int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1306

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1308

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1329

ret = a6xx_gmu_secure_init(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1346

status = a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

140

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

141

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1411

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1412

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1422

if (a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET))

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1425

a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1437

adreno_gpu->funcs->bus_halt(adreno_gpu, a6xx_gpu->hung);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1478

int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1480

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1481

struct msm_gpu *gpu = &a6xx_gpu->base.base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1530

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1531

struct drm_device *dev = a6xx_gpu->base.base.dev;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

160

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

161

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1836

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1837

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1935

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1936

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1978

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1980

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2085

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2086

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2108

void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2110

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2111

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2188

int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2191

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2193

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2274

int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2277

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2279

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

24

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

25

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

254

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

255

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

262

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

263

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

293

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

294

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

395

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

396

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

435

if (completion_done(&a6xx_gpu->base.fault_coredump_done))

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

442

wait_for_completion(&a6xx_gpu->base.fault_coredump_done);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

460

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

461

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

548

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

549

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

566

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

567

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

639

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

640

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

670

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

671

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

803

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

804

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

865

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

866

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

930

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

931

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

950

a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

97

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

98

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

100

ret = fenced_write(a6xx_gpu, offset, lower_32_bits(value), mask);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1018

a6xx_gpu->has_whereami = true;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1049

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1051

if (!a6xx_gpu->sqe_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1052

a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1053

adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1055

if (IS_ERR(a6xx_gpu->sqe_bo)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1056

int ret = PTR_ERR(a6xx_gpu->sqe_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1058

a6xx_gpu->sqe_bo = NULL;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1065

msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1066

if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1067

msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1068

drm_gem_object_put(a6xx_gpu->sqe_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

107

ret = fenced_write(a6xx_gpu, offset + 1, upper_32_bits(value), mask);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1070

a6xx_gpu->sqe_bo = NULL;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1075

if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1076

a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1077

adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1079

if (IS_ERR(a6xx_gpu->aqe_bo)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1080

int ret = PTR_ERR(a6xx_gpu->aqe_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1082

a6xx_gpu->aqe_bo = NULL;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1089

msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw");

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1096

if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) &&

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1097

!a6xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1098

a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1101

gpu->vm, &a6xx_gpu->shadow_bo,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1102

&a6xx_gpu->shadow_iova);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1104

if (IS_ERR(a6xx_gpu->shadow))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1105

return PTR_ERR(a6xx_gpu->shadow);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1107

msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1110

a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PWRUP_REGLIST_SIZE,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1112

gpu->vm, &a6xx_gpu->pwrup_reglist_bo,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1113

&a6xx_gpu->pwrup_reglist_iova);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1115

if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1116

return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1118

msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist");

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

115

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1176

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1177

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

118

if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1184

ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1330

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1435

gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1451

if (a6xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1453

shadowptr(a6xx_gpu, gpu->rb[0]));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1455

a6xx_gpu->shadow[i] = 0;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1467

a6xx_gpu->cur_ring = gpu->rb[0];

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1475

if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1477

a6xx_gpu->pwrup_reglist_emitted = true;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

152

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1525

a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1527

if (a6xx_gpu->gmu.legacy) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1529

a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1544

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1547

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1549

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

155

if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1564

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1565

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

157

OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

158

OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1584

a6xx_gpu->hung = true;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1634

a6xx_gpu->hung = false;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

165

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

180

if (!a6xx_in_preempt(a6xx_gpu)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

181

if (a6xx_gpu->cur_ring == ring)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

182

a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1870

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1875

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, on);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1881

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1882

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1952

static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1954

llcc_slice_deactivate(a6xx_gpu->llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1955

llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1958

static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1960

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1964

if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1967

if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1968

u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1986

if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1987

if (!a6xx_gpu->have_mmu500) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1988

u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2002

if (!a6xx_gpu->have_mmu500) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2003

a6xx_cx_misc_write(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2010

a6xx_cx_misc_rmw(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2018

static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2020

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2023

if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2026

if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2027

u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2044

llcc_slice_activate(a6xx_gpu->htw_llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2047

static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2050

if (adreno_has_gmu_wrapper(&a6xx_gpu->base))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2053

llcc_slice_putd(a6xx_gpu->llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2054

llcc_slice_putd(a6xx_gpu->htw_llc_slice);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2058

struct a6xx_gpu *a6xx_gpu, bool is_a7xx)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2061

if (adreno_has_gmu_wrapper(&a6xx_gpu->base))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2064

a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2065

a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2130

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2137

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2138

ret = a6xx_gmu_resume(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2139

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2146

a8xx_llc_activate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2148

a7xx_llc_activate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2150

a6xx_llc_activate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2158

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2159

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2168

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

22

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2204

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2208

a6xx_llc_activate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2217

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2222

a6xx_llc_deactivate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2226

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2227

ret = a6xx_gmu_stop(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2228

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2232

if (a6xx_gpu->shadow_bo)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2234

a6xx_gpu->shadow[i] = 0;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2244

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2245

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2250

a6xx_llc_deactivate(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2254

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2269

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

227

static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2271

if (a6xx_gpu->shadow_bo)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2273

a6xx_gpu->shadow[i] = 0;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2288

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2290

return a6xx_gpu->cur_ring;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2296

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2298

if (a6xx_gpu->sqe_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2299

msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

230

bool sysprof = msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2300

drm_gem_object_put(a6xx_gpu->sqe_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2303

if (a6xx_gpu->aqe_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2304

msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2305

drm_gem_object_put(a6xx_gpu->aqe_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2308

if (a6xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2309

msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2310

drm_gem_object_put(a6xx_gpu->shadow_bo);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2313

a6xx_llc_slices_destroy(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2315

a6xx_gmu_remove(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2319

kfree(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2325

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

233

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2331

busy_cycles = gmu_read64(&a6xx_gpu->gmu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2342

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2344

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2346

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2353

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2360

if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2384

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2386

if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2387

return a6xx_gpu->shadow[ring->id];

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2471

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2477

WARN_ON(!a6xx_gpu->pwrup_reglist_emitted);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2479

struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2482

(3 * a6xx_gpu->dynamic_sel_reglist_offset);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2489

lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2555

struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2565

lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset + nr_regs;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2591

static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

26

count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2602

*speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2610

static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2617

ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2648

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2654

return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2664

struct a6xx_gpu *a6xx_gpu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2672

a6xx_gpu = kzalloc_obj(*a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2673

if (!a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2676

adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2693

mutex_init(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2694

spin_lock_init(&a6xx_gpu->aperture_lock);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

27

count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2712

a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2719

a6xx_gpu->have_mmu500 = (phandle &&

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2723

if (is_a7xx || !a6xx_gpu->have_mmu500)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2724

a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2726

a6xx_gpu->cx_misc_mmio = NULL;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2728

ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2730

a6xx_llc_slices_destroy(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2731

kfree(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2741

a6xx_destroy(&(a6xx_gpu->base.base));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2746

if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2758

ret = a6xx_gmu_wrapper_init(a6xx_gpu, node);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2760

ret = a6xx_gmu_init(a6xx_gpu, node);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2762

a6xx_destroy(&(a6xx_gpu->base.base));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

2773

a6xx_destroy(&(a6xx_gpu->base.base));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

28

temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

317

if (adreno_is_a7xx(&a6xx_gpu->base) || adreno_is_a8xx(&a6xx_gpu->base)) {

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

358

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

364

a6xx_set_pagetable(a6xx_gpu, ring, submit);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

439

struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

453

a6xx_gpu->preempt_iova[ring->id]));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

455

a6xx_gpu->preempt_iova[ring->id]));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

468

preempt_postamble = a6xx_gpu->preempt_postamble_iova;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

474

a6xx_gpu->preempt_postamble_len) |

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

482

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

496

a6xx_set_pagetable(a6xx_gpu, ring, submit);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

503

a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

52

static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

54

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

56

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

609

a6xx_gpu->last_seqno[ring->id] = submit->seqno;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

638

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

639

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

671

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

673

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

675

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

806

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

809

void *ptr = a6xx_gpu->pwrup_reglist_ptr;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

872

a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

878

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

888

a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

927

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

96

int a6xx_fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u64 value, u32 mask, bool is_64b)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

965

OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

967

OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova));

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

979

static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

982

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

127

#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

253

static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

255

return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

258

static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

260

return readl(a6xx_gpu->cx_misc_mmio + (reg << 2));

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

263

static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

265

writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2));

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

271

int a6xx_gmu_resume(struct a6xx_gpu *gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

272

int a6xx_gmu_stop(struct a6xx_gpu *gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

281

int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

282

int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

283

void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

292

struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

299

static inline bool a6xx_in_preempt(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

307

int preempt_state = atomic_read(&a6xx_gpu->preempt_state);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

328

int a6xx_fenced_write(struct a6xx_gpu *gpu, u32 offset, u64 value, u32 mask, bool is_64b);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

342

void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1197

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1198

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1231

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1258

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1291

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1292

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

148

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

155

if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu))

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1586

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1602

a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1603

a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi);

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

1604

a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

115

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

125

if (completion_done(&a6xx_gpu->base.fault_coredump_done))

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

132

wait_for_completion(&a6xx_gpu->base.fault_coredump_done);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

331

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

332

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

802

struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

803

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

103

set_preempt_state(a6xx_gpu, PREEMPT_FAULTED);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

110

a6xx_gpu->cur_ring = a6xx_gpu->next_ring;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

111

a6xx_gpu->next_ring = NULL;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

113

set_preempt_state(a6xx_gpu, PREEMPT_FINISH);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

115

update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

117

set_preempt_state(a6xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

121

trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

133

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

141

struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[i];

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

145

record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

15

struct a6xx_gpu *a6xx_gpu = timer_container_of(a6xx_gpu, t,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

158

set_preempt_state(a6xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

160

spin_lock_init(&a6xx_gpu->eval_lock);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

163

a6xx_gpu->cur_ring = gpu->rb[0];

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

169

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

17

struct msm_gpu *gpu = &a6xx_gpu->base.base;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

183

spin_lock_irqsave(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

189

if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) {

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

190

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

194

cntl = A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL(a6xx_gpu->preempt_level);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

196

if (a6xx_gpu->skip_save_restore)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

199

if (a6xx_gpu->uses_gmem)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

20

if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED))

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

211

if (!ring || (a6xx_gpu->cur_ring == ring)) {

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

212

set_preempt_state(a6xx_gpu, PREEMPT_FINISH);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

213

update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

214

set_preempt_state(a6xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

215

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

219

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

224

a6xx_gpu->preempt_smmu[ring->id];

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

225

struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[ring->id];

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

243

trace_msm_gpu_preemption_trigger(a6xx_gpu->cur_ring->id, ring->id);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

250

a6xx_fenced_write(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

251

REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, a6xx_gpu->preempt_smmu_iova[ring->id],

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

254

a6xx_fenced_write(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

256

a6xx_gpu->preempt_iova[ring->id], BIT(1), true);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

258

a6xx_gpu->next_ring = ring;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

261

mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

266

if (!sysprof && !a6xx_gpu->postamble_enabled)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

267

preempt_prepare_postamble(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

269

if (sysprof && a6xx_gpu->postamble_enabled)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

27

static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

270

preempt_disable_postamble(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

273

set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

276

a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl, BIT(1), false);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

279

static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

282

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

29

u32 *postamble = a6xx_gpu->preempt_postamble_ptr;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

301

a6xx_gpu->preempt_bo[ring->id] = bo;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

302

a6xx_gpu->preempt_iova[ring->id] = iova;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

303

a6xx_gpu->preempt[ring->id] = ptr;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

319

a6xx_gpu->preempt_smmu_bo[ring->id] = bo;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

320

a6xx_gpu->preempt_smmu_iova[ring->id] = iova;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

321

a6xx_gpu->preempt_smmu[ring->id] = ptr;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

349

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

353

msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->vm);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

359

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

367

if (preempt_init_ring(a6xx_gpu, gpu->rb[i]))

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

372

a6xx_gpu->preempt_level = 1;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

373

a6xx_gpu->uses_gmem = 1;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

374

a6xx_gpu->skip_save_restore = 1;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

376

a6xx_gpu->preempt_postamble_ptr = msm_gem_kernel_new(gpu->dev,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

379

gpu->vm, &a6xx_gpu->preempt_postamble_bo,

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

380

&a6xx_gpu->preempt_postamble_iova);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

382

if (IS_ERR(a6xx_gpu->preempt_postamble_ptr))

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

385

preempt_prepare_postamble(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

387

timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

46

a6xx_gpu->preempt_postamble_len = count;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

48

a6xx_gpu->postamble_enabled = true;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

51

static void preempt_disable_postamble(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

53

u32 *postamble = a6xx_gpu->preempt_postamble_ptr;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

59

*postamble = PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1));

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

61

a6xx_gpu->postamble_enabled = false;

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

71

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

76

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, on);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

83

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

86

if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING))

drivers/gpu/drm/msm/adreno/a6xx_preempt.c

90

timer_delete(&a6xx_gpu->preempt_timer);

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

11

static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu,

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

14

enum a6xx_preempt_state cur = atomic_cmpxchg(&a6xx_gpu->preempt_state,

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

24

static inline void set_preempt_state(struct a6xx_gpu *gpu,

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

39

static inline void update_wptr(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring)

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

49

a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

61

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

72

if (!empty && ring == a6xx_gpu->cur_ring)

drivers/gpu/drm/msm/adreno/a6xx_preempt.h

73

empty = ring->memptrs->fence == a6xx_gpu->last_seqno[i];

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1026

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1027

u32 slice = a8xx_get_first_slice(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

103

a6xx_gpu->slice_mask = slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

107

slice_mask &= a6xx_cx_misc_read(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

110

a6xx_gpu->slice_mask = slice_mask;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1123

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1141

gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

125

static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1258

void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1260

struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1263

if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1264

u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

127

return ffs(a6xx_gpu->slice_mask) - 1;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1282

llcc_slice_activate(a6xx_gpu->htw_llc_slice);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1318

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1322

count_hi = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1323

count_lo = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_L);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1324

temp = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

133

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1333

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1339

busy_cycles = gmu_read64(&a6xx_gpu->gmu,

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

136

if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

171

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

184

if (!a6xx_in_preempt(a6xx_gpu)) {

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

185

if (a6xx_gpu->cur_ring == ring)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

186

a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

199

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

200

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

22

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

27

if (a6xx_gpu->cached_aperture == val)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

32

a6xx_gpu->cached_aperture = val;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

38

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

399

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

40

spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

401

void *ptr = a6xx_gpu->pwrup_reglist_ptr;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

460

a8xx_get_first_slice(a6xx_gpu),

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

467

a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

476

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

48

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

486

a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

496

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

50

spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

533

OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

535

OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

624

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

625

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

631

ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

636

a6xx_gpu->cached_aperture = UINT_MAX;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

676

gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1,

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

73

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

756

gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

757

if (a6xx_gpu->aqe_iova)

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

758

gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

765

gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0]));

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

77

spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

771

a6xx_gpu->shadow[i] = 0;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

774

a6xx_gpu->cur_ring = gpu->rb[0];

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

80

spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

824

if (!a6xx_gpu->pwrup_reglist_emitted) {

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

826

a6xx_gpu->pwrup_reglist_emitted = true;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

839

a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

853

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

856

mutex_lock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

858

mutex_unlock(&a6xx_gpu->gmu.lock);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

872

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

873

struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

88

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

882

a6xx_gpu->hung = true;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

934

a6xx_gpu->hung = false;

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

96

if (a6xx_gpu->slice_mask)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

102

trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

11

static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

114

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

122

struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[i];

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

126

record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

13

u32 *postamble = a6xx_gpu->preempt_postamble_ptr;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

139

set_preempt_state(a6xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

141

spin_lock_init(&a6xx_gpu->eval_lock);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

144

a6xx_gpu->cur_ring = gpu->rb[0];

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

150

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

164

spin_lock_irqsave(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

170

if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) {

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

171

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

175

cntl = A8XX_CP_CONTEXT_SWITCH_CNTL_LEVEL(a6xx_gpu->preempt_level);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

177

if (a6xx_gpu->skip_save_restore)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

180

if (a6xx_gpu->uses_gmem)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

192

if (!ring || (a6xx_gpu->cur_ring == ring)) {

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

193

set_preempt_state(a6xx_gpu, PREEMPT_FINISH);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

194

update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

195

set_preempt_state(a6xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

196

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

200

spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

205

a6xx_gpu->preempt_smmu[ring->id];

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

206

struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[ring->id];

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

224

trace_msm_gpu_preemption_trigger(a6xx_gpu->cur_ring->id, ring->id);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

231

a6xx_fenced_write(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

232

REG_A8XX_CP_CONTEXT_SWITCH_SMMU_INFO, a6xx_gpu->preempt_smmu_iova[ring->id],

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

235

a6xx_fenced_write(a6xx_gpu,

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

237

a6xx_gpu->preempt_iova[ring->id], BIT(1), true);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

239

a6xx_gpu->next_ring = ring;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

242

mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

247

if (!sysprof && !a6xx_gpu->postamble_enabled)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

248

preempt_prepare_postamble(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

250

if (sysprof && a6xx_gpu->postamble_enabled)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

251

preempt_disable_postamble(a6xx_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

254

set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

257

a6xx_fenced_write(a6xx_gpu, REG_A8XX_CP_CONTEXT_SWITCH_CNTL, cntl, BIT(1), false);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

30

a6xx_gpu->preempt_postamble_len = count;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

32

a6xx_gpu->postamble_enabled = true;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

35

static void preempt_disable_postamble(struct a6xx_gpu *a6xx_gpu)

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

37

u32 *postamble = a6xx_gpu->preempt_postamble_ptr;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

43

*postamble = PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1));

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

45

a6xx_gpu->postamble_enabled = false;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

55

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

57

gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, on);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

64

struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

67

if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING))

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

71

timer_delete(&a6xx_gpu->preempt_timer);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

84

set_preempt_state(a6xx_gpu, PREEMPT_FAULTED);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

91

a6xx_gpu->cur_ring = a6xx_gpu->next_ring;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

92

a6xx_gpu->next_ring = NULL;

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

94

set_preempt_state(a6xx_gpu, PREEMPT_FINISH);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

96

update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a8xx_preempt.c

98

set_preempt_state(a6xx_gpu, PREEMPT_NONE);