a5psw_reg_readl
ret = a5psw_reg_readl(a5psw, A5PSW_MDIO_DATA) & A5PSW_MDIO_DATA_MASK;
status = a5psw_reg_readl(a5psw, A5PSW_MDIO_CFG_STATUS);
u32 reg = a5psw_reg_readl(a5psw, A5PSW_AUTH_PORT(port));
cmd_cfg = a5psw_reg_readl(a5psw, A5PSW_CMD_CFG(port));
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
lk_data.lo = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_LO);
vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
reg = a5psw_reg_readl(a5psw, vlan_res_off);
reg_lo = a5psw_reg_readl(a5psw, offset + A5PSW_PORT_OFFSET(port));
reg_hi = a5psw_reg_readl(a5psw, A5PSW_STATS_HIWORD);
reg = a5psw_reg_readl(a5psw, offset);