drivers/net/dsa/rzn1_a5psw.c
102
static void a5psw_port_pattern_set(struct a5psw *a5psw, int port, int pattern,
drivers/net/dsa/rzn1_a5psw.c
1042
static int a5psw_mdio_wait_busy(struct a5psw *a5psw)
drivers/net/dsa/rzn1_a5psw.c
1047
err = readl_poll_timeout(a5psw->base + A5PSW_MDIO_CFG_STATUS, status,
drivers/net/dsa/rzn1_a5psw.c
1051
dev_err(a5psw->dev, "MDIO command timeout\n");
drivers/net/dsa/rzn1_a5psw.c
1058
struct a5psw *a5psw = bus->priv;
drivers/net/dsa/rzn1_a5psw.c
1066
a5psw_reg_writel(a5psw, A5PSW_MDIO_COMMAND, cmd);
drivers/net/dsa/rzn1_a5psw.c
1068
ret = a5psw_mdio_wait_busy(a5psw);
drivers/net/dsa/rzn1_a5psw.c
1072
ret = a5psw_reg_readl(a5psw, A5PSW_MDIO_DATA) & A5PSW_MDIO_DATA_MASK;
drivers/net/dsa/rzn1_a5psw.c
1074
status = a5psw_reg_readl(a5psw, A5PSW_MDIO_CFG_STATUS);
drivers/net/dsa/rzn1_a5psw.c
1084
struct a5psw *a5psw = bus->priv;
drivers/net/dsa/rzn1_a5psw.c
1090
a5psw_reg_writel(a5psw, A5PSW_MDIO_COMMAND, cmd);
drivers/net/dsa/rzn1_a5psw.c
1091
a5psw_reg_writel(a5psw, A5PSW_MDIO_DATA, phy_data);
drivers/net/dsa/rzn1_a5psw.c
1093
return a5psw_mdio_wait_busy(a5psw);
drivers/net/dsa/rzn1_a5psw.c
1096
static int a5psw_mdio_config(struct a5psw *a5psw, u32 mdio_freq)
drivers/net/dsa/rzn1_a5psw.c
110
a5psw_reg_rmw(a5psw, A5PSW_RXMATCH_CONFIG(port),
drivers/net/dsa/rzn1_a5psw.c
1102
rate = clk_get_rate(a5psw->hclk);
drivers/net/dsa/rzn1_a5psw.c
1106
dev_err(a5psw->dev, "MDIO clock div %ld out of range\n", div);
drivers/net/dsa/rzn1_a5psw.c
1112
a5psw_reg_writel(a5psw, A5PSW_MDIO_CFG_STATUS, cfgstatus);
drivers/net/dsa/rzn1_a5psw.c
1117
static int a5psw_probe_mdio(struct a5psw *a5psw, struct device_node *node)
drivers/net/dsa/rzn1_a5psw.c
1119
struct device *dev = a5psw->dev;
drivers/net/dsa/rzn1_a5psw.c
1127
ret = a5psw_mdio_config(a5psw, mdio_freq);
drivers/net/dsa/rzn1_a5psw.c
1138
bus->priv = a5psw;
drivers/net/dsa/rzn1_a5psw.c
114
static void a5psw_port_mgmtfwd_set(struct a5psw *a5psw, int port, bool enable)
drivers/net/dsa/rzn1_a5psw.c
1142
a5psw->mii_bus = bus;
drivers/net/dsa/rzn1_a5psw.c
1147
static void a5psw_pcs_free(struct a5psw *a5psw)
drivers/net/dsa/rzn1_a5psw.c
1151
for (i = 0; i < ARRAY_SIZE(a5psw->pcs); i++) {
drivers/net/dsa/rzn1_a5psw.c
1152
if (a5psw->pcs[i])
drivers/net/dsa/rzn1_a5psw.c
1153
miic_destroy(a5psw->pcs[i]);
drivers/net/dsa/rzn1_a5psw.c
1157
static int a5psw_pcs_get(struct a5psw *a5psw)
drivers/net/dsa/rzn1_a5psw.c
1164
ports = of_get_child_by_name(a5psw->dev->of_node, "ethernet-ports");
drivers/net/dsa/rzn1_a5psw.c
1178
if (reg >= ARRAY_SIZE(a5psw->pcs)) {
drivers/net/dsa/rzn1_a5psw.c
1183
pcs = miic_create(a5psw->dev, pcs_node);
drivers/net/dsa/rzn1_a5psw.c
1185
dev_err(a5psw->dev, "Failed to create PCS for port %d\n",
drivers/net/dsa/rzn1_a5psw.c
1191
a5psw->pcs[reg] = pcs;
drivers/net/dsa/rzn1_a5psw.c
120
a5psw_port_pattern_set(a5psw, port, A5PSW_PATTERN_MGMTFWD, enable);
drivers/net/dsa/rzn1_a5psw.c
1202
a5psw_pcs_free(a5psw);
drivers/net/dsa/rzn1_a5psw.c
1212
struct a5psw *a5psw;
drivers/net/dsa/rzn1_a5psw.c
1215
a5psw = devm_kzalloc(dev, sizeof(*a5psw), GFP_KERNEL);
drivers/net/dsa/rzn1_a5psw.c
1216
if (!a5psw)
drivers/net/dsa/rzn1_a5psw.c
1219
a5psw->dev = dev;
drivers/net/dsa/rzn1_a5psw.c
1220
mutex_init(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
1221
spin_lock_init(&a5psw->reg_lock);
drivers/net/dsa/rzn1_a5psw.c
1222
a5psw->base = devm_platform_ioremap_resource(pdev, 0);
drivers/net/dsa/rzn1_a5psw.c
1223
if (IS_ERR(a5psw->base))
drivers/net/dsa/rzn1_a5psw.c
1224
return PTR_ERR(a5psw->base);
drivers/net/dsa/rzn1_a5psw.c
1226
a5psw->bridged_ports = BIT(A5PSW_CPU_PORT);
drivers/net/dsa/rzn1_a5psw.c
1228
ret = a5psw_pcs_get(a5psw);
drivers/net/dsa/rzn1_a5psw.c
123
static void a5psw_port_tx_enable(struct a5psw *a5psw, int port, bool enable)
drivers/net/dsa/rzn1_a5psw.c
1232
a5psw->hclk = devm_clk_get_enabled(dev, "hclk");
drivers/net/dsa/rzn1_a5psw.c
1233
if (IS_ERR(a5psw->hclk)) {
drivers/net/dsa/rzn1_a5psw.c
1235
ret = PTR_ERR(a5psw->hclk);
drivers/net/dsa/rzn1_a5psw.c
1239
a5psw->clk = devm_clk_get_enabled(dev, "clk");
drivers/net/dsa/rzn1_a5psw.c
1240
if (IS_ERR(a5psw->clk)) {
drivers/net/dsa/rzn1_a5psw.c
1242
ret = PTR_ERR(a5psw->clk);
drivers/net/dsa/rzn1_a5psw.c
1248
ret = a5psw_probe_mdio(a5psw, mdio);
drivers/net/dsa/rzn1_a5psw.c
1256
ds = &a5psw->ds;
drivers/net/dsa/rzn1_a5psw.c
1261
ds->priv = a5psw;
drivers/net/dsa/rzn1_a5psw.c
1272
a5psw_pcs_free(a5psw);
drivers/net/dsa/rzn1_a5psw.c
1279
struct a5psw *a5psw = platform_get_drvdata(pdev);
drivers/net/dsa/rzn1_a5psw.c
1281
if (!a5psw)
drivers/net/dsa/rzn1_a5psw.c
1284
dsa_unregister_switch(&a5psw->ds);
drivers/net/dsa/rzn1_a5psw.c
1285
a5psw_pcs_free(a5psw);
drivers/net/dsa/rzn1_a5psw.c
1290
struct a5psw *a5psw = platform_get_drvdata(pdev);
drivers/net/dsa/rzn1_a5psw.c
1292
if (!a5psw)
drivers/net/dsa/rzn1_a5psw.c
1295
dsa_switch_shutdown(&a5psw->ds);
drivers/net/dsa/rzn1_a5psw.c
136
a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, mask, reg);
drivers/net/dsa/rzn1_a5psw.c
139
static void a5psw_port_enable_set(struct a5psw *a5psw, int port, bool enable)
drivers/net/dsa/rzn1_a5psw.c
146
a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, A5PSW_PORT_ENA_TX_RX(port),
drivers/net/dsa/rzn1_a5psw.c
150
static int a5psw_lk_execute_ctrl(struct a5psw *a5psw, u32 *ctrl)
drivers/net/dsa/rzn1_a5psw.c
154
a5psw_reg_writel(a5psw, A5PSW_LK_ADDR_CTRL, *ctrl);
drivers/net/dsa/rzn1_a5psw.c
156
ret = readl_poll_timeout(a5psw->base + A5PSW_LK_ADDR_CTRL, *ctrl,
drivers/net/dsa/rzn1_a5psw.c
160
dev_err(a5psw->dev, "LK_CTRL timeout waiting for BUSY bit\n");
drivers/net/dsa/rzn1_a5psw.c
165
static void a5psw_port_fdb_flush(struct a5psw *a5psw, int port)
drivers/net/dsa/rzn1_a5psw.c
169
mutex_lock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
170
a5psw_lk_execute_ctrl(a5psw, &ctrl);
drivers/net/dsa/rzn1_a5psw.c
171
mutex_unlock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
174
static void a5psw_port_authorize_set(struct a5psw *a5psw, int port,
drivers/net/dsa/rzn1_a5psw.c
177
u32 reg = a5psw_reg_readl(a5psw, A5PSW_AUTH_PORT(port));
drivers/net/dsa/rzn1_a5psw.c
184
a5psw_reg_writel(a5psw, A5PSW_AUTH_PORT(port), reg);
drivers/net/dsa/rzn1_a5psw.c
189
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
191
a5psw_port_authorize_set(a5psw, port, false);
drivers/net/dsa/rzn1_a5psw.c
192
a5psw_port_enable_set(a5psw, port, false);
drivers/net/dsa/rzn1_a5psw.c
198
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
200
a5psw_port_authorize_set(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
201
a5psw_port_enable_set(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
208
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
211
a5psw_reg_writel(a5psw, A5PSW_FRM_LENGTH(port), new_mtu);
drivers/net/dsa/rzn1_a5psw.c
246
struct a5psw *a5psw = dp->ds->priv;
drivers/net/dsa/rzn1_a5psw.c
251
return a5psw->pcs[dp->index];
drivers/net/dsa/rzn1_a5psw.c
265
struct a5psw *a5psw = dp->ds->priv;
drivers/net/dsa/rzn1_a5psw.c
269
cmd_cfg = a5psw_reg_readl(a5psw, A5PSW_CMD_CFG(port));
drivers/net/dsa/rzn1_a5psw.c
271
a5psw_reg_writel(a5psw, A5PSW_CMD_CFG(port), cmd_cfg);
drivers/net/dsa/rzn1_a5psw.c
284
struct a5psw *a5psw = dp->ds->priv;
drivers/net/dsa/rzn1_a5psw.c
297
a5psw_reg_writel(a5psw, A5PSW_CMD_CFG(dp->index), cmd_cfg);
drivers/net/dsa/rzn1_a5psw.c
302
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
307
rate = clk_get_rate(a5psw->clk);
drivers/net/dsa/rzn1_a5psw.c
316
a5psw_reg_writel(a5psw, A5PSW_LK_AGETIME, agetime);
drivers/net/dsa/rzn1_a5psw.c
321
static void a5psw_port_learning_set(struct a5psw *a5psw, int port, bool learn)
drivers/net/dsa/rzn1_a5psw.c
326
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg);
drivers/net/dsa/rzn1_a5psw.c
329
static void a5psw_port_rx_block_set(struct a5psw *a5psw, int port, bool block)
drivers/net/dsa/rzn1_a5psw.c
334
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg);
drivers/net/dsa/rzn1_a5psw.c
337
static void a5psw_flooding_set_resolution(struct a5psw *a5psw, int port,
drivers/net/dsa/rzn1_a5psw.c
346
a5psw_reg_rmw(a5psw, offsets[i], BIT(port),
drivers/net/dsa/rzn1_a5psw.c
350
static void a5psw_port_set_standalone(struct a5psw *a5psw, int port,
drivers/net/dsa/rzn1_a5psw.c
353
a5psw_port_learning_set(a5psw, port, !standalone);
drivers/net/dsa/rzn1_a5psw.c
354
a5psw_flooding_set_resolution(a5psw, port, !standalone);
drivers/net/dsa/rzn1_a5psw.c
355
a5psw_port_mgmtfwd_set(a5psw, port, standalone);
drivers/net/dsa/rzn1_a5psw.c
363
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
366
if (a5psw->br_dev && bridge.dev != a5psw->br_dev) {
drivers/net/dsa/rzn1_a5psw.c
372
a5psw->br_dev = bridge.dev;
drivers/net/dsa/rzn1_a5psw.c
373
a5psw_port_set_standalone(a5psw, port, false);
drivers/net/dsa/rzn1_a5psw.c
375
a5psw->bridged_ports |= BIT(port);
drivers/net/dsa/rzn1_a5psw.c
383
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
385
a5psw->bridged_ports &= ~BIT(port);
drivers/net/dsa/rzn1_a5psw.c
387
a5psw_port_set_standalone(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
390
if (a5psw->bridged_ports == BIT(A5PSW_CPU_PORT))
drivers/net/dsa/rzn1_a5psw.c
391
a5psw->br_dev = NULL;
drivers/net/dsa/rzn1_a5psw.c
410
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
420
if (!(a5psw->bridged_ports & BIT(port)))
drivers/net/dsa/rzn1_a5psw.c
425
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN,
drivers/net/dsa/rzn1_a5psw.c
431
a5psw_reg_rmw(a5psw, A5PSW_UCAST_DEF_MASK, BIT(port), val);
drivers/net/dsa/rzn1_a5psw.c
436
a5psw_reg_rmw(a5psw, A5PSW_MCAST_DEF_MASK, BIT(port), val);
drivers/net/dsa/rzn1_a5psw.c
441
a5psw_reg_rmw(a5psw, A5PSW_BCAST_DEF_MASK, BIT(port), val);
drivers/net/dsa/rzn1_a5psw.c
451
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
476
a5psw_port_learning_set(a5psw, port, learning_enabled);
drivers/net/dsa/rzn1_a5psw.c
477
a5psw_port_rx_block_set(a5psw, port, !rx_enabled);
drivers/net/dsa/rzn1_a5psw.c
478
a5psw_port_tx_enable(a5psw, port, tx_enabled);
drivers/net/dsa/rzn1_a5psw.c
483
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
485
a5psw_port_fdb_flush(a5psw, port);
drivers/net/dsa/rzn1_a5psw.c
488
static int a5psw_lk_execute_lookup(struct a5psw *a5psw, union lk_data *lk_data,
drivers/net/dsa/rzn1_a5psw.c
494
a5psw_reg_writel(a5psw, A5PSW_LK_DATA_LO, lk_data->lo);
drivers/net/dsa/rzn1_a5psw.c
495
a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data->hi);
drivers/net/dsa/rzn1_a5psw.c
498
ret = a5psw_lk_execute_ctrl(a5psw, &ctrl);
drivers/net/dsa/rzn1_a5psw.c
511
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
521
mutex_lock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
524
ret = a5psw_lk_execute_lookup(a5psw, &lk_data, &entry);
drivers/net/dsa/rzn1_a5psw.c
528
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
drivers/net/dsa/rzn1_a5psw.c
540
a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi);
drivers/net/dsa/rzn1_a5psw.c
543
ret = a5psw_lk_execute_ctrl(a5psw, ®);
drivers/net/dsa/rzn1_a5psw.c
549
a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
drivers/net/dsa/rzn1_a5psw.c
553
mutex_unlock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
562
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
571
mutex_lock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
573
ret = a5psw_lk_execute_lookup(a5psw, &lk_data, &entry);
drivers/net/dsa/rzn1_a5psw.c
577
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
drivers/net/dsa/rzn1_a5psw.c
593
a5psw_reg_writel(a5psw, A5PSW_LK_DATA_HI, lk_data.hi);
drivers/net/dsa/rzn1_a5psw.c
601
ret = a5psw_lk_execute_ctrl(a5psw, ®);
drivers/net/dsa/rzn1_a5psw.c
608
a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
drivers/net/dsa/rzn1_a5psw.c
612
mutex_unlock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
620
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
625
mutex_lock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
630
ret = a5psw_lk_execute_ctrl(a5psw, ®);
drivers/net/dsa/rzn1_a5psw.c
634
lk_data.hi = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_HI);
drivers/net/dsa/rzn1_a5psw.c
640
lk_data.lo = a5psw_reg_readl(a5psw, A5PSW_LK_DATA_LO);
drivers/net/dsa/rzn1_a5psw.c
648
mutex_unlock(&a5psw->lk_lock);
drivers/net/dsa/rzn1_a5psw.c
660
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
663
a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE_ENA, BIT(port),
drivers/net/dsa/rzn1_a5psw.c
667
a5psw_reg_rmw(a5psw, A5PSW_VLAN_VERIFY, mask, val);
drivers/net/dsa/rzn1_a5psw.c
672
static int a5psw_find_vlan_entry(struct a5psw *a5psw, u16 vid)
drivers/net/dsa/rzn1_a5psw.c
679
vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
drivers/net/dsa/rzn1_a5psw.c
687
static int a5psw_new_vlan_res_entry(struct a5psw *a5psw, u16 newvid)
drivers/net/dsa/rzn1_a5psw.c
694
vlan_res = a5psw_reg_readl(a5psw, A5PSW_VLAN_RES(i));
drivers/net/dsa/rzn1_a5psw.c
697
a5psw_reg_writel(a5psw, A5PSW_VLAN_RES(i), vlan_res);
drivers/net/dsa/rzn1_a5psw.c
705
static void a5psw_port_vlan_tagged_cfg(struct a5psw *a5psw,
drivers/net/dsa/rzn1_a5psw.c
71
static void a5psw_reg_writel(struct a5psw *a5psw, int offset, u32 value)
drivers/net/dsa/rzn1_a5psw.c
718
a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
drivers/net/dsa/rzn1_a5psw.c
719
reg = a5psw_reg_readl(a5psw, vlan_res_off);
drivers/net/dsa/rzn1_a5psw.c
720
a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
drivers/net/dsa/rzn1_a5psw.c
724
a5psw_reg_writel(a5psw, vlan_res_off, reg);
drivers/net/dsa/rzn1_a5psw.c
727
static void a5psw_port_vlan_cfg(struct a5psw *a5psw, unsigned int vlan_res_id,
drivers/net/dsa/rzn1_a5psw.c
73
writel(value, a5psw->base + offset);
drivers/net/dsa/rzn1_a5psw.c
736
a5psw_reg_rmw(a5psw, A5PSW_VLAN_RES(vlan_res_id), mask, reg);
drivers/net/dsa/rzn1_a5psw.c
745
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
749
vlan_res_id = a5psw_find_vlan_entry(a5psw, vid);
drivers/net/dsa/rzn1_a5psw.c
751
vlan_res_id = a5psw_new_vlan_res_entry(a5psw, vid);
drivers/net/dsa/rzn1_a5psw.c
756
a5psw_port_vlan_cfg(a5psw, vlan_res_id, port, true);
drivers/net/dsa/rzn1_a5psw.c
758
a5psw_port_vlan_tagged_cfg(a5psw, vlan_res_id, port, true);
drivers/net/dsa/rzn1_a5psw.c
76
static u32 a5psw_reg_readl(struct a5psw *a5psw, int offset)
drivers/net/dsa/rzn1_a5psw.c
765
a5psw_reg_writel(a5psw, A5PSW_SYSTEM_TAGINFO(port), vid);
drivers/net/dsa/rzn1_a5psw.c
773
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
777
vlan_res_id = a5psw_find_vlan_entry(a5psw, vid);
drivers/net/dsa/rzn1_a5psw.c
78
return readl(a5psw->base + offset);
drivers/net/dsa/rzn1_a5psw.c
781
a5psw_port_vlan_cfg(a5psw, vlan_res_id, port, false);
drivers/net/dsa/rzn1_a5psw.c
782
a5psw_port_vlan_tagged_cfg(a5psw, vlan_res_id, port, false);
drivers/net/dsa/rzn1_a5psw.c
787
static u64 a5psw_read_stat(struct a5psw *a5psw, u32 offset, int port)
drivers/net/dsa/rzn1_a5psw.c
791
reg_lo = a5psw_reg_readl(a5psw, offset + A5PSW_PORT_OFFSET(port));
drivers/net/dsa/rzn1_a5psw.c
793
reg_hi = a5psw_reg_readl(a5psw, A5PSW_STATS_HIWORD);
drivers/net/dsa/rzn1_a5psw.c
81
static void a5psw_reg_rmw(struct a5psw *a5psw, int offset, u32 mask, u32 val)
drivers/net/dsa/rzn1_a5psw.c
813
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
817
data[u] = a5psw_read_stat(a5psw, a5psw_stats[u].offset, port);
drivers/net/dsa/rzn1_a5psw.c
831
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
833
#define RD(name) a5psw_read_stat(a5psw, A5PSW_##name, port)
drivers/net/dsa/rzn1_a5psw.c
85
spin_lock(&a5psw->reg_lock);
drivers/net/dsa/rzn1_a5psw.c
87
reg = a5psw_reg_readl(a5psw, offset);
drivers/net/dsa/rzn1_a5psw.c
871
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
873
#define RD(name) a5psw_read_stat(a5psw, A5PSW_##name, port)
drivers/net/dsa/rzn1_a5psw.c
893
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
896
stat = a5psw_read_stat(a5psw, A5PSW_aTxPAUSEMACCtrlFrames, port);
drivers/net/dsa/rzn1_a5psw.c
898
stat = a5psw_read_stat(a5psw, A5PSW_aRxPAUSEMACCtrlFrames, port);
drivers/net/dsa/rzn1_a5psw.c
90
a5psw_reg_writel(a5psw, offset, reg);
drivers/net/dsa/rzn1_a5psw.c
902
static void a5psw_vlan_setup(struct a5psw *a5psw, int port)
drivers/net/dsa/rzn1_a5psw.c
911
a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE, A5PSW_VLAN_IN_MODE_PORT(port),
drivers/net/dsa/rzn1_a5psw.c
919
a5psw_reg_rmw(a5psw, A5PSW_VLAN_OUT_MODE,
drivers/net/dsa/rzn1_a5psw.c
92
spin_unlock(&a5psw->reg_lock);
drivers/net/dsa/rzn1_a5psw.c
925
struct a5psw *a5psw = ds->priv;
drivers/net/dsa/rzn1_a5psw.c
933
dev_err(a5psw->dev, "Invalid CPU port\n");
drivers/net/dsa/rzn1_a5psw.c
940
a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg);
drivers/net/dsa/rzn1_a5psw.c
943
a5psw_reg_writel(a5psw, A5PSW_PATTERN_CTRL(A5PSW_PATTERN_MGMTFWD),
drivers/net/dsa/rzn1_a5psw.c
949
a5psw_reg_writel(a5psw, A5PSW_MGMT_TAG_CFG, reg);
drivers/net/dsa/rzn1_a5psw.c
955
a5psw_reg_writel(a5psw, A5PSW_LK_CTRL, reg);
drivers/net/dsa/rzn1_a5psw.c
957
ret = readl_poll_timeout(a5psw->base + A5PSW_LK_CTRL, reg,
drivers/net/dsa/rzn1_a5psw.c
961
dev_err(a5psw->dev, "Failed to clear lookup table\n");
drivers/net/dsa/rzn1_a5psw.c
967
a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
drivers/net/dsa/rzn1_a5psw.c
972
a5psw_reg_writel(a5psw, A5PSW_VLAN_RES(vlan), reg);
drivers/net/dsa/rzn1_a5psw.c
979
a5psw_reg_writel(a5psw, A5PSW_CMD_CFG(port),
drivers/net/dsa/rzn1_a5psw.c
983
a5psw_port_enable_set(a5psw, port, dsa_port_is_cpu(dp));
drivers/net/dsa/rzn1_a5psw.c
990
a5psw_flooding_set_resolution(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
991
a5psw_port_learning_set(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
996
a5psw_port_set_standalone(a5psw, port, true);
drivers/net/dsa/rzn1_a5psw.c
998
a5psw_vlan_setup(a5psw, port);
