_il_wr
_il_wr(il, CSR_INT, inta);
_il_wr(il, CSR_FH_INT_STATUS, inta_fh);
_il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
_il_wr(il, CSR_RESET, 0);
_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
_il_wr(il, CSR_INT, 0xFFFFFFFF);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
_il_wr(il, CSR_INT, 0xFFFFFFFF);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
_il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
_il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
_il_wr(il, FH39_RCSR_CONFIG(0), 0);
_il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
_il_wr(il, CSR_UCODE_DRV_GP1_SET,
_il_wr(il, CSR_UCODE_DRV_GP1_SET,
_il_wr(il, CSR_UCODE_DRV_GP1_CLR,
_il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
_il_wr(il, CSR_INT, inta);
_il_wr(il, CSR_FH_INT_STATUS, inta_fh);
_il_wr(il, CSR_RESET, 0);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR,
_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
_il_wr(il, CSR_INT, 0xFFFFFFFF);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
_il_wr(il, CSR_INT, 0xFFFFFFFF);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
_il_wr(il, CSR_INT, 0xFFFFFFFF);
_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
_il_wr(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK);
_il_wr(il, CSR_LED_REG, CSR_LED_REG_TRUN_ON);
_il_wr(il, HBUS_TARG_MEM_RADDR, addr);
_il_wr(il, HBUS_TARG_MEM_WADDR, addr);
_il_wr(il, HBUS_TARG_MEM_WDAT, val);
_il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
_il_wr(il, CSR_INT, 0xffffffff);
_il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
_il_wr(il, CSR_INT_MASK, 0x00000000);
_il_wr(il, CSR_EEPROM_REG,
_il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
_il_wr(il, reg, _il_rd(il, reg) & ~mask);
_il_wr(il, reg, _il_rd(il, reg) | mask);
_il_wr(il, reg, value);
_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
_il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
_il_wr(il, HBUS_TARG_PRPH_WDAT, val);
_il_wr(il, CSR_INT_MASK, 0x00000000);
_il_wr(il, CSR_INT, 0xffffffff);
_il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
_il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
_il_wr(il, CSR_INT_MASK, il->inta_mask);