_il_rd
inta = _il_rd(il, CSR_INT);
inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
inta_mask = _il_rd(il, CSR_INT_MASK);
inta = _il_rd(il, CSR_INT);
inta_mask = _il_rd(il, CSR_INT_MASK);
inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
val = _il_rd(il, HBUS_TARG_MEM_RDAT);
val = _il_rd(il, HBUS_TARG_MEM_RDAT);
if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
return _il_rd(il, CSR_UCODE_DRV_GP2);
_il_rd(il, FH39_TSSR_CBB_BASE);
ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
_il_rd(il, CSR_UCODE_DRV_GP1);
inta = _il_rd(il, CSR_INT);
inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
inta_mask = _il_rd(il, CSR_INT_MASK);
if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
inta = _il_rd(il, CSR_INT);
inta_mask = _il_rd(il, CSR_INT_MASK);
inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
il->hw_rev = _il_rd(il, CSR_HW_REV);
il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
reg = _il_rd(il, CSR_LED_REG);
val = _il_rd(il, HBUS_TARG_MEM_RDAT);
val = _il_rd(il, HBUS_TARG_MEM_RDAT);
value = _il_rd(il, HBUS_TARG_MEM_RDAT);
reg = _il_rd(il, CSR_UCODE_DRV_GP1);
reg = _il_rd(il, CSR_UCODE_DRV_GP1);
if ((_il_rd(il, addr) & mask) == (bits & mask))
if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
inta = _il_rd(il, CSR_INT);
inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
u32 gp = _il_rd(il, CSR_EEPROM_GP);
r = _il_rd(il, CSR_EEPROM_REG);
val = _il_rd(il, CSR_GP_CNTRL);
_il_wr(il, reg, _il_rd(il, reg) & ~mask);
_il_wr(il, reg, _il_rd(il, reg) | mask);
value = _il_rd(il, reg);
return _il_rd(il, HBUS_TARG_PRPH_RDAT);
_il_rd(il, CSR_GP_CNTRL) & CSR_GP_REG_POWER_SAVE_STATUS_MSK;