Symbol: access_ereg
drivers/net/phy/microchip_t1.c
1069
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
drivers/net/phy/microchip_t1.c
1074
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
418
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
drivers/net/phy/microchip_t1.c
423
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
drivers/net/phy/microchip_t1.c
444
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
470
return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
drivers/net/phy/microchip_t1.c
487
ret = access_ereg(phydev, cmd_seq[i].mode,
drivers/net/phy/microchip_t1.c
703
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
drivers/net/phy/microchip_t1.c
709
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
722
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
drivers/net/phy/microchip_t1.c
734
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
drivers/net/phy/microchip_t1.c
740
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
752
irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
849
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
drivers/net/phy/microchip_t1.c
855
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
drivers/net/phy/microchip_t1.c
888
rc = access_ereg(phydev, cable_test[i].mode,
drivers/net/phy/microchip_t1.c
928
gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
931
pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
933
neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
935
pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
937
neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
drivers/net/phy/microchip_t1.c
988
rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
drivers/net/phy/microchip_t1.c
995
rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,