a7
result->as64.high = res.a7;
cpu_reg(ctxt, 7) = res->a7;
cfi_st a7, PT_R11, \docfi
cfi_ld a7, PT_R11, \docfi
| fsave -(a7)
| frestore (a7)+
# if it's a fmove out instruction, we don't have to fix a7
# if exception occurred in user mode, then we have to restore a7 in case it
# if it's a fmove out instruction, we don't have to fix a7
movel #0xFC098000, %a7
movel #0x0, (%a7)
register op_t a0, a1, a2, a3, a4, a5, a6, a7;
a7 = ((op_t *) srcp)[7];
((op_t *) dstp)[7] = a7;
int64_t a4, int64_t a5, int64_t a6, int64_t a7,
return __opal_call(a0, a1, a2, a3, a4, a5, a6, a7, opcode, msr);
ret = __opal_call_trace(a0, a1, a2, a3, a4, a5, a6, a7, opcode, msr);
ret = __opal_call(a0, a1, a2, a3, a4, a5, a6, a7, opcode, msr);
int64_t a4, int64_t a5, int64_t a6, int64_t a7); \
int64_t a4, int64_t a5, int64_t a6, int64_t a7) \
return opal_call(a0, a1, a2, a3, a4, a5, a6, a7, opcode); \
s64 a4, s64 a5, s64 a6, s64 a7,
args[7] = a7;
s64 a4, s64 a5, s64 a6, s64 a7,
__trace_opal_entry(a0, a1, a2, a3, a4, a5, a6, a7, opcode);
ret = __opal_call(a0, a1, a2, a3, a4, a5, a6, a7, opcode, msr);
s64 a4, s64 a5, s64 a6, s64 a7,
int64_t a4, int64_t a5, int64_t a6, int64_t a7, int64_t opcode)
REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
regs->a7 = (unsigned long) cregs->a7;
compat_ulong_t a7;
cregs->a7 = (compat_ulong_t) regs->a7;
unsigned long a7;
unsigned long a7;
offsetof(struct pt_regs, a7),
unsigned long a7;
return regs->a7;
regs->a7 = nr;
unsigned long a7;
OFFSET(PT_A7, pt_regs, a7);
OFFSET(KVM_ARCH_GUEST_A7, kvm_vcpu_arch, guest_context.a7);
OFFSET(KVM_ARCH_HOST_A7, kvm_vcpu_arch, host_context.a7);
DEFINE(FREGS_A7, offsetof(struct __arch_ftrace_regs, a7));
{DBG_REG_A7, GDB_SIZEOF_REG, offsetof(struct pt_regs, a7)},
regs->a5, regs->a6, regs->a7);
REG_OFFSET_NAME(a7),
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
regs->a7 = __NR_restart_syscall;
long syscall = regs->a7;
run->riscv_sbi.extension_id = cp->a7;
sbi_ext = kvm_vcpu_sbi_find_ext(vcpu, cp->a7);
if (cp->a7 >= SBI_EXT_0_1_SET_TIMER &&
cp->a7 <= SBI_EXT_0_1_SHUTDOWN)
switch (cp->a7) {
if (cp->a7 == SBI_EXT_0_1_REMOTE_FENCE_I)
else if (cp->a7 == SBI_EXT_0_1_REMOTE_SFENCE_VMA) {
#define abi_arg1 a7
#define abi_arg5 a7
witlb a3, a7
idtlb a7
iitlb a7
addi a7, a2, 5 - XCHAL_SPANNING_WAY
wdtlb a3, a7
be64_to_cpua(18, c6, 37, 8a, cb, a7, d8, 7d),
be64_to_cpua(6a, c3, f3, 7a, d1, fa, e7, a7),
be64_to_cpua(da, a7, cd, 26, 28, 76, 3b, 52),
be64_to_cpua(71, d0, e9, ca, a7, c0, cb, aa),
be64_to_cpua(dd, 15, bb, d6, 8c, a7, 03, 78),
be64_to_cpua(8a, fa, 54, 93, 29, a7, 70, 86),
be64_to_cpua(eb, a7, 80, 26, dc, f9, 3a, 44),
unsigned long a6, unsigned long a7,
.a6 = data->data3, .a7 = data->data4,
data->data4 = ret.a7;
ret.a7);
str_fragment_from_reg(smccc_soc_id_name + 8 * 6, res.a7);
priv->status.error_location = res->a7;
unsigned long a6, unsigned long a7,
arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res);
unsigned long a0, a1, a2, a3, a4, a5, a6, a7;
a7 = 0;
ctrl->invoke_fn(a0, a1, a2, a3, a4, a5, a6, a7, &res);
unsigned long a6, unsigned long a7,
arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res);
c->a7 = FIELD_GET(GENMASK(14, 7), val3) - 128;
dev_dbg(yas5xx->dev, "a7 = %d\n", c->a7);
dev_dbg(yas5xx->dev, "a7 = %d\n", c->a7);
s8 a2, a3, a4, a6, a7, a8;
h[2] = (c->k * (c->a7 * s[0] + c->a8 * s[1] + c->a9 * s[2])) / half_range;
*zo = c->k * ((c->a7 * sx + c->a8 * sy + c->a9 * sz) / 10);
c->a7 = FIELD_GET(GENMASK_ULL(35, 29), val) - 64;
#define AOM_CDF9(a0, a1, a2, a3, a4, a5, a6, a7) \
AOM_ICDF(a4), AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7)
#define AOM_CDF10(a0, a1, a2, a3, a4, a5, a6, a7, a8) \
AOM_ICDF(a4), AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8)
#define AOM_CDF11(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9) \
AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9)
#define AOM_CDF12(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) \
AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), AOM_ICDF(a10)
#define AOM_CDF13(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) \
AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), AOM_ICDF(a10), AOM_ICDF(a11)
#define AOM_CDF14(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) \
AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \
#define AOM_CDF15(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) \
AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \
#define AOM_CDF16(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) \
AOM_ICDF(a5), AOM_ICDF(a6), AOM_ICDF(a7), AOM_ICDF(a8), AOM_ICDF(a9), \
__u8 a7;
__u8 a7;
u32 a7;
unsigned long a6, unsigned long a7,
arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res);
unsigned long a6, unsigned long a7,
arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res);
param.a4, param.a5, param.a6, param.a7,
unsigned long a7;
unsigned long a5, unsigned long a6, unsigned long a7,
unsigned long a5, unsigned long a6, unsigned long a7,
unsigned long a5, unsigned long a6, unsigned long a7,
#define __declare_arg_9(a0, a1, a2, a3, a4, a5, a6, a7, res) \
typeof(a7) __a7 = a7; \
register typeof(a7) arg7 asm("r7") = __a7
u32 a7 = get_unaligned_le32(s+28);
h[8] = (a6>>12) | ((a7&((1<< 6)-1))<<20); /* (32-12) + 6 = 20+ 6 = 26 */
h[9] = (a7>> 6)&((1<<25)-1); /* 25 */
#define __PT_PARM8_REG a7
{ "a7", offsetof(struct user_regs_struct, a7) },
REG_DWARFNUM_NAME(a7, 55),
long a6, __u64 a7, uintptr_t a8, int a9, short a10,
usdt12_args[6] = a7;
unsigned long a7;
core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7));
core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
id = RISCV_CORE_REG(regs.a7);
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7):
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7),
# define SYSCALL_NUM(_regs) (_regs).a7