drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1240

ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1285

if (a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET))

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1965

a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

206

a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

508

return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

553

ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

1258

ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

268

int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

1185

a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

514

ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);