drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

118

if (a5xx_gpu->pm4_bo) {

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

119

msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

120

drm_gem_object_put(a5xx_gpu->pm4_bo);

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

121

a5xx_gpu->pm4_bo = NULL;

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

124

if (a5xx_gpu->pfp_bo) {

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

125

msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

126

drm_gem_object_put(a5xx_gpu->pfp_bo);

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

127

a5xx_gpu->pfp_bo = NULL;

drivers/gpu/drm/msm/adreno/a5xx_debugfs.c

99

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1038

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1044

if (a5xx_gpu->pm4_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1045

msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1046

drm_gem_object_put(a5xx_gpu->pm4_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1049

if (a5xx_gpu->pfp_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1050

msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1051

drm_gem_object_put(a5xx_gpu->pfp_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1054

if (a5xx_gpu->gpmu_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1055

msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1056

drm_gem_object_put(a5xx_gpu->gpmu_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1059

if (a5xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1060

msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1061

drm_gem_object_put(a5xx_gpu->shadow_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1065

kfree(a5xx_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1084

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1086

if (ring != a5xx_gpu->cur_ring) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

114

a5xx_gpu->last_seqno[ring->id] = submit->seqno;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

130

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1402

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1431

if (a5xx_gpu->has_whereami)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1433

a5xx_gpu->shadow[i] = 0;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

151

OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

152

OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1667

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1669

return a5xx_gpu->cur_ring;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1685

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1687

if (a5xx_gpu->has_whereami)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1688

return a5xx_gpu->shadow[ring->id];

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1731

struct a5xx_gpu *a5xx_gpu = NULL;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1737

a5xx_gpu = kzalloc_obj(*a5xx_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1738

if (!a5xx_gpu)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1741

adreno_gpu = &a5xx_gpu->base;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1746

a5xx_gpu->lm_leakage = 0x4E001A;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

1757

a5xx_destroy(&(a5xx_gpu->base.base));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

218

a5xx_gpu->last_seqno[ring->id] = submit->seqno;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

24

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

26

if (a5xx_gpu->has_whereami) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

28

OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

29

OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

37

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

522

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

534

OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id]));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

535

OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id]));

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

563

static void a5xx_ucode_check_version(struct a5xx_gpu *a5xx_gpu,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

577

a5xx_gpu->has_whereami = true;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

585

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

588

if (!a5xx_gpu->pm4_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

589

a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

590

adreno_gpu->fw[ADRENO_FW_PM4], &a5xx_gpu->pm4_iova);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

593

if (IS_ERR(a5xx_gpu->pm4_bo)) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

594

ret = PTR_ERR(a5xx_gpu->pm4_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

595

a5xx_gpu->pm4_bo = NULL;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

601

msm_gem_object_set_name(a5xx_gpu->pm4_bo, "pm4fw");

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

604

if (!a5xx_gpu->pfp_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

605

a5xx_gpu->pfp_bo = adreno_fw_create_bo(gpu,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

606

adreno_gpu->fw[ADRENO_FW_PFP], &a5xx_gpu->pfp_iova);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

608

if (IS_ERR(a5xx_gpu->pfp_bo)) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

609

ret = PTR_ERR(a5xx_gpu->pfp_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

610

a5xx_gpu->pfp_bo = NULL;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

616

msm_gem_object_set_name(a5xx_gpu->pfp_bo, "pfpfw");

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

617

a5xx_ucode_check_version(a5xx_gpu, a5xx_gpu->pfp_bo);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

62

if (a5xx_gpu->cur_ring == ring && !a5xx_in_preempt(a5xx_gpu))

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

620

if (a5xx_gpu->has_whereami) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

621

if (!a5xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

622

a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

625

gpu->vm, &a5xx_gpu->shadow_bo,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

626

&a5xx_gpu->shadow_iova);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

628

if (IS_ERR(a5xx_gpu->shadow))

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

629

return PTR_ERR(a5xx_gpu->shadow);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

631

msm_gem_object_set_name(a5xx_gpu->shadow_bo, "shadow");

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

69

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

698

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

930

gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, a5xx_gpu->pm4_iova);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

931

gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, a5xx_gpu->pfp_iova);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

946

if (a5xx_gpu->shadow_bo) {

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

948

shadowptr(a5xx_gpu, gpu->rb[0]));

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

154

#define shadowptr(a5xx_gpu, ring) ((a5xx_gpu)->shadow_iova + \

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

169

static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu)

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

171

int preempt_state = atomic_read(&a5xx_gpu->preempt_state);

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

51

#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)

drivers/gpu/drm/msm/adreno/a5xx_power.c

125

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_power.c

141

gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage);

drivers/gpu/drm/msm/adreno/a5xx_power.c

223

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_power.c

226

if (!a5xx_gpu->gpmu_dwords)

drivers/gpu/drm/msm/adreno/a5xx_power.c

235

OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova));

drivers/gpu/drm/msm/adreno/a5xx_power.c

236

OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova));

drivers/gpu/drm/msm/adreno/a5xx_power.c

237

OUT_RING(ring, a5xx_gpu->gpmu_dwords);

drivers/gpu/drm/msm/adreno/a5xx_power.c

327

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_power.c

336

if (a5xx_gpu->gpmu_bo)

drivers/gpu/drm/msm/adreno/a5xx_power.c

367

&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);

drivers/gpu/drm/msm/adreno/a5xx_power.c

371

msm_gem_object_set_name(a5xx_gpu->gpmu_bo, "gpmufw");

drivers/gpu/drm/msm/adreno/a5xx_power.c

388

msm_gem_put_vaddr(a5xx_gpu->gpmu_bo);

drivers/gpu/drm/msm/adreno/a5xx_power.c

389

a5xx_gpu->gpmu_dwords = dwords;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

110

spin_lock_irqsave(&a5xx_gpu->preempt_start_lock, flags);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

116

if (!try_preempt_state(a5xx_gpu, PREEMPT_NONE, PREEMPT_START))

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

12

static inline bool try_preempt_state(struct a5xx_gpu *a5xx_gpu,

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

126

if (!ring || (a5xx_gpu->cur_ring == ring)) {

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

139

set_preempt_state(a5xx_gpu, PREEMPT_ABORT);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

140

update_wptr(gpu, a5xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

141

set_preempt_state(a5xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

145

spin_unlock_irqrestore(&a5xx_gpu->preempt_start_lock, flags);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

149

a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

15

enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state,

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

154

a5xx_gpu->preempt_iova[ring->id]);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

156

a5xx_gpu->next_ring = ring;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

159

mod_timer(&a5xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

162

set_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

172

spin_unlock_irqrestore(&a5xx_gpu->preempt_start_lock, flags);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

179

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

182

if (!try_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING))

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

186

timer_delete(&a5xx_gpu->preempt_timer);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

196

set_preempt_state(a5xx_gpu, PREEMPT_FAULTED);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

203

a5xx_gpu->cur_ring = a5xx_gpu->next_ring;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

204

a5xx_gpu->next_ring = NULL;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

206

update_wptr(gpu, a5xx_gpu->cur_ring);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

208

set_preempt_state(a5xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

220

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

224

a5xx_gpu->cur_ring = gpu->rb[0];

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

231

a5xx_gpu->preempt[i]->data = 0;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

232

a5xx_gpu->preempt[i]->info = 0;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

233

a5xx_gpu->preempt[i]->wptr = 0;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

234

a5xx_gpu->preempt[i]->rptr = 0;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

235

a5xx_gpu->preempt[i]->rbase = gpu->rb[i]->iova;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

236

a5xx_gpu->preempt[i]->rptr_addr = shadowptr(a5xx_gpu, gpu->rb[i]);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

243

set_preempt_state(a5xx_gpu, PREEMPT_NONE);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

246

static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu,

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

249

struct adreno_gpu *adreno_gpu = &a5xx_gpu->base;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

25

static inline void set_preempt_state(struct a5xx_gpu *gpu,

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

275

a5xx_gpu->preempt_bo[ring->id] = bo;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

276

a5xx_gpu->preempt_counters_bo[ring->id] = counters_bo;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

277

a5xx_gpu->preempt_iova[ring->id] = iova;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

278

a5xx_gpu->preempt[ring->id] = ptr;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

295

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

299

msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

300

msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i], gpu->vm);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

307

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

315

if (preempt_init_ring(a5xx_gpu, gpu->rb[i])) {

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

327

spin_lock_init(&a5xx_gpu->preempt_start_lock);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

328

timer_setup(&a5xx_gpu->preempt_timer, a5xx_preempt_timer, 0);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

59

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

69

if (!empty && ring == a5xx_gpu->cur_ring)

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

70

empty = ring->memptrs->fence == a5xx_gpu->last_seqno[i];

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

82

struct a5xx_gpu *a5xx_gpu = timer_container_of(a5xx_gpu, t,

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

84

struct msm_gpu *gpu = &a5xx_gpu->base.base;

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

87

if (!try_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED))

drivers/gpu/drm/msm/adreno/a5xx_preempt.c

98

struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);