a5psw_reg_rmw
a5psw_reg_rmw(a5psw, A5PSW_RXMATCH_CONFIG(port),
a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, mask, reg);
a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, A5PSW_PORT_ENA_TX_RX(port),
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg);
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg);
a5psw_reg_rmw(a5psw, offsets[i], BIT(port),
a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN,
a5psw_reg_rmw(a5psw, A5PSW_UCAST_DEF_MASK, BIT(port), val);
a5psw_reg_rmw(a5psw, A5PSW_MCAST_DEF_MASK, BIT(port), val);
a5psw_reg_rmw(a5psw, A5PSW_BCAST_DEF_MASK, BIT(port), val);
a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE_ENA, BIT(port),
a5psw_reg_rmw(a5psw, A5PSW_VLAN_VERIFY, mask, val);
a5psw_reg_rmw(a5psw, A5PSW_VLAN_RES(vlan_res_id), mask, reg);
a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE, A5PSW_VLAN_IN_MODE_PORT(port),
a5psw_reg_rmw(a5psw, A5PSW_VLAN_OUT_MODE,