__raw_readb
extern u8 __raw_readb(const volatile void __iomem *addr);
#define __raw_readb __raw_readb
ret = __raw_readb(addr);
return __raw_readb(addr);
EXPORT_SYMBOL(__raw_readb);
ret = __raw_readb(addr);
return __raw_readb(addr);
*(u8 *) to = __raw_readb(from);
#define readb_relaxed(c) __raw_readb(c)
#define __raw_readb __raw_readb
#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
#define __raw_readb __raw_readb
#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
return __raw_readb(OMAP1_IO_ADDRESS(pa));
return (unsigned int)__raw_readb(up->membase + offset);
#define __raw_readb __raw_readb
#define __raw_readb __raw_readb
#define readb __raw_readb
#define mcf_read8 __raw_readb
#define readb __raw_readb
#define in_8(a) __raw_readb(a)
return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
__raw_readb((__force unsigned *)(addr))
#define __raw_readb __raw_readb
#define ltq_r8(reg) __raw_readb(reg)
return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
*(u8 *)dst = __raw_readb(addr);
#define __raw_readb __raw_readb
#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
pgdr = __raw_readb(PGDR);
stbcr = __raw_readb(STBCR);
stbcr2 = __raw_readb(STBCR2);
stbcr = __raw_readb(STBCR);
v8 = __raw_readb(DACR);
v8 = __raw_readb(SCPDR);
data = __raw_readb(addr);
sw_value = (0x0ff & (~__raw_readb(PA_STATUS)));
__raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10;
min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10;
day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10;
mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10;
year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10
+ (__raw_readb(RTC_YEA100 ) & 0xf) * 100
+ (__raw_readb(RTC_YEA1000) & 0xf) * 1000;
} while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10);
if (!(__raw_readb(RTC_CTL) & RTC_BUSY))
type, __raw_readb(chan->reg_base + PCI_REVISION_ID));
#define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
return __raw_readb(WTCNT_R);
return __raw_readb(WTCSR_R);
return __raw_readb(RSTCSR_R);
v = __raw_readb(DACR);
v = __raw_readb(DACR);
#define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
#define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
csr = __raw_readb(ADCSR);
csr = __raw_readb(ADCSR);
return (((__raw_readb(ADDRAH + off) << 8) |
__raw_readb(ADDRAL + off)) >> 6);
__raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
data = __raw_readb(SCPDR);
sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
byte = __raw_readb(addr);
byte = __raw_readb(addr);
insn = __raw_readb(current_insn++);
cie->return_address_reg = __raw_readb(p);
tmp = __raw_readb(src_addr);
#define readb_be(__addr) __raw_readb(__addr)
#define __raw_readb __raw_readb
return __raw_readb(addr);
w = (__raw_readb(addr) << 24);
w |= (__raw_readb(addr) << 16);
w |= (__raw_readb(addr) << 8);
w |= (__raw_readb(addr) << 0);
*pb++ = __raw_readb(addr);
*pb++ = __raw_readb(addr);
*buf = __raw_readb(addr);
return (__raw_readb(GDROM_ALTSTATUS_REG) & 0x80) != 0;
return (__raw_readb(GDROM_ALTSTATUS_REG) & 0x88) == 8;
while ((__raw_readb(GDROM_ALTSTATUS_REG) & 0x80) &&
return __raw_readb(GDROM_ERROR_REG);
char sense = __raw_readb(GDROM_ERROR_REG);
return (__raw_readb(GDROM_ERROR_REG) & 0xF0) == 0x60 ?
gd.status = __raw_readb(GDROM_STATUSCOMMAND_REG);
gd.status = __raw_readb(GDROM_STATUSCOMMAND_REG);
while (__raw_readb(GDROM_DMA_STATUS_REG) &&
edev->name[i] = __raw_readb(edev->addr + REG_DATA + i);
val = __raw_readb(addr++);
*s++ = __raw_readb(PCDR);
*s++ = __raw_readb(PFDR);
*s++ = __raw_readb(PGDR);
*s++ = __raw_readb(PHDR);
if (__raw_readb(PHDR) & PHDR_TS_PEN_DOWN) {
scpdr = __raw_readb(SCPDR);
scpdr = __raw_readb(SCPDR);
scpdr = __raw_readb(SCPDR);
touched = __raw_readb(PHDR) & PHDR_TS_PEN_DOWN;
#define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
#define __fs_in8(addr) __raw_readb(addr)
#define READ_U8(addr) __raw_readb(addr)
data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
__raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
__raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */
(void)__raw_readb(ptr); /* Defeat write posting */
value = intc_set_field_from_handle(__raw_readb(ptr), data, h);
(void)__raw_readb(ptr); /* Defeat write posting */
return intc_get_field_from_handle(__raw_readb(ptr), h);
__raw_readb(addr);
*buf = __raw_readb(addr);
*buf = __raw_readb(addr);
return __raw_readb(port->membase + ATMEL_US_RHR);
pkt.raw[i++] = __raw_readb(dreg);
__raw_readb((ep)->dev->regs + ofs_##reg(ep))
u8 data = __raw_readb(addr + offset);
dst[index] = __raw_readb(fifo);
#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
val = __raw_readb(wdt->base);
val = __raw_readb(wdt->base);
cfg = __raw_readb(wd_cfg_reg);
__raw_writeb(__raw_readb(wdog) | 1, wdog);
#ifndef __raw_readb
#define __raw_readb __raw_readb
val = __raw_readb(addr);
val = __raw_readb(addr);
u8 x = __raw_readb(addr);
val = __raw_readb(PCI_IOBASE + addr);
#define __raw_readb __raw_readb
u8 __raw_readb(const volatile void __iomem *addr);
return __raw_readb(addr);
r.x[0] = __raw_readb(map->virt + ofs);
u8 data = __raw_readb(addr);
*(u8 *)dst = __raw_readb(src);
*(u8 *)dst = __raw_readb(src);
val = __raw_readb(addr);
val = __raw_readb(addr);
u8 x = __raw_readb(addr);
#ifndef __raw_readb
#define __raw_readb __raw_readb