arch/loongarch/include/asm/kvm_csr.h

208

unsigned long _mask = mask;

arch/loongarch/include/asm/kvm_csr.h

210

csr->csrs[gid] &= ~_mask;

arch/loongarch/include/asm/kvm_csr.h

211

csr->csrs[gid] |= val & _mask;

arch/mips/include/asm/kvm_host.h

463

unsigned long _mask = mask; \

arch/mips/include/asm/kvm_host.h

464

cop0->reg[(_reg)][(sel)] &= ~_mask; \

arch/mips/include/asm/kvm_host.h

465

cop0->reg[(_reg)][(sel)] |= val & _mask; \

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

77

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

78

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

105

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

106

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

105

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

106

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

108

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

109

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

108

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

109

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

111

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

112

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

150

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7724.c

151

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

69

#define DIV4(_reg, _bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7734.c

70

SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

62

#define DIV4(_bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7757.c

63

SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

66

#define DIV4(_bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7785.c

67

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

67

#define DIV4(_bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

68

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

arch/sh/kernel/cpu/sh4a/clock-shx3.c

61

#define DIV4(_bit, _mask, _flags) \

arch/sh/kernel/cpu/sh4a/clock-shx3.c

62

SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

drivers/bcma/sprom.c

185

#define SPEX(_field, _offset, _mask, _shift) \

drivers/bcma/sprom.c

186

bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))

drivers/bcma/sprom.c

188

#define SPEX32(_field, _offset, _mask, _shift) \

drivers/bcma/sprom.c

190

sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))

drivers/bcma/sprom.c

192

#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \

drivers/bcma/sprom.c

194

SPEX(_field[0], _offset + 0, _mask, _shift); \

drivers/bcma/sprom.c

195

SPEX(_field[1], _offset + 2, _mask, _shift); \

drivers/bcma/sprom.c

196

SPEX(_field[2], _offset + 4, _mask, _shift); \

drivers/bcma/sprom.c

197

SPEX(_field[3], _offset + 6, _mask, _shift); \

drivers/bcma/sprom.c

198

SPEX(_field[4], _offset + 8, _mask, _shift); \

drivers/bcma/sprom.c

199

SPEX(_field[5], _offset + 10, _mask, _shift); \

drivers/bcma/sprom.c

200

SPEX(_field[6], _offset + 12, _mask, _shift); \

drivers/bcma/sprom.c

201

SPEX(_field[7], _offset + 14, _mask, _shift); \

drivers/clk/baikal-t1/ccu-div.c

338

#define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) { \

drivers/clk/baikal-t1/ccu-div.c

340

.mask = _mask \

drivers/clk/baikal-t1/ccu-div.c

43

#define CCU_DIV_CLKDIV_MAX(_mask) \

drivers/clk/baikal-t1/ccu-div.c

44

((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)

drivers/clk/baikal-t1/ccu-pll.c

324

#define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \

drivers/clk/baikal-t1/ccu-pll.c

328

.mask = _mask \

drivers/clk/baikal-t1/ccu-pll.c

331

#define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \

drivers/clk/baikal-t1/ccu-pll.c

336

.mask = _mask, \

drivers/clk/meson/axg-audio.c

94

#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \

drivers/clk/meson/axg-audio.c

97

.mask = (_mask), \

drivers/clk/meson/c3-peripherals.c

51

#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \

drivers/clk/meson/c3-peripherals.c

52

MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

drivers/clk/meson/meson-clkc-utils.h

52

#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \

drivers/clk/meson/meson-clkc-utils.h

57

.mask = (_mask), \

drivers/clk/meson/s4-peripherals.c

66

#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \

drivers/clk/meson/s4-peripherals.c

67

MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

drivers/clk/meson/t7-peripherals.c

50

#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \

drivers/clk/meson/t7-peripherals.c

51

MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

drivers/clk/nxp/clk-lpc32xx.c

1113

#define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \

drivers/clk/nxp/clk-lpc32xx.c

1124

.mask = (_mask), \

drivers/clk/spacemit/ccu_mix.h

49

#define CCU_GATE_INIT(_mask) { .mask = _mask }

drivers/clk/spacemit/ccu_mix.h

53

#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted }

drivers/clk/st/clkgen.h

38

#define CLKGEN_FIELD(_offset, _mask, _shift) { \

drivers/clk/st/clkgen.h

40

.mask = _mask, \

drivers/clk/uniphier/clk-uniphier.h

69

#define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \

drivers/clk/uniphier/clk-uniphier.h

79

.mask = (_mask) \

drivers/crypto/ccp/ccp-dmaengine.c

21

#define CCP_DMA_WIDTH(_mask) \

drivers/crypto/ccp/ccp-dmaengine.c

23

u64 mask = _mask + 1; \

drivers/dpll/zl3073x/core.h

116

#define HWREG_SEQ_ITEM(_addr, _value, _mask, _wait) \

drivers/dpll/zl3073x/core.h

119

.value = FIELD_PREP_CONST(_mask, _value), \

drivers/dpll/zl3073x/core.h

120

.mask = _mask, \

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

36

.type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

59

.type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

76

.type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h

33

.type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h

41

.type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

35

gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

230

u32 _mask, u32 _data, u32 _copy)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

236

u32 mask = _mask | _copy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

237

u32 data = (_data & _mask) | (reg->data & _copy);

drivers/gpu/drm/panel/panel-sitronix-st7701.c

93

#define CFIELD_PREP(_mask, _val) \

drivers/gpu/drm/panel/panel-sitronix-st7701.c

94

(((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

203

uint32_t _offset, uint32_t _mask, uint32_t v,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

214

mask = reg->mask & _mask;

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

21

#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

24

.mask = _mask, \

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

30

#define VOP_REG(off, _mask, _shift) \

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

31

_VOP_REG(off, _mask, _shift, false, true)

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

33

#define VOP_REG_SYNC(off, _mask, _shift) \

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

34

_VOP_REG(off, _mask, _shift, false, false)

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

36

#define VOP_REG_MASK_SYNC(off, _mask, _shift) \

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

37

_VOP_REG(off, _mask, _shift, true, false)

drivers/gpu/drm/xe/xe_gt_throttle.c

156

#define THROTTLE_ATTR_RO(name, _mask) \

drivers/gpu/drm/xe/xe_gt_throttle.c

159

.mask = _mask, \

drivers/gpu/drm/xe/xe_gt_throttle.c

162

#define THROTTLE_ATTR_RO_FUNC(name, _mask, _show) \

drivers/gpu/drm/xe/xe_gt_throttle.c

165

.mask = _mask, \

drivers/hwtracing/intel_th/gth.c

225

#define OUTPUT_PARM(_name, _mask, _r, _w, _what) \

drivers/hwtracing/intel_th/gth.c

229

.mask = (_mask), \

drivers/iio/accel/mma9553.c

922

#define MMA9553_PEDOMETER_CHANNEL(_type, _mask) { \

drivers/iio/accel/mma9553.c

926

_mask, \

drivers/iio/adc/max1363.c

196

#define MAX1363_MODE_SINGLE(_num, _mask) { \

drivers/iio/adc/max1363.c

200

.modemask[0] = _mask, \

drivers/iio/adc/max1363.c

203

#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \

drivers/iio/adc/max1363.c

207

.modemask[0] = _mask, \

drivers/iio/adc/max1363.c

211

#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \

drivers/iio/adc/max1363.c

215

.modemask[0] = _mask \

drivers/iio/adc/max1363.c

218

#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \

drivers/iio/adc/max1363.c

222

.modemask[0] = _mask \

drivers/iio/adc/max1363.c

226

#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \

drivers/iio/adc/max1363.c

230

.modemask[0] = _mask \

drivers/iio/adc/max1363.c

234

#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \

drivers/iio/adc/max1363.c

238

.modemask[0] = _mask \

drivers/iio/adc/qcom-spmi-adc5.c

501

#define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \

drivers/iio/adc/qcom-spmi-adc5.c

506

.info_mask = _mask, \

drivers/iio/adc/qcom-spmi-vadc.c

523

#define VADC_CHAN(_dname, _type, _mask, _pre, _scale) \

drivers/iio/adc/qcom-spmi-vadc.c

528

.info_mask = _mask, \

drivers/iio/adc/qcom-spmi-vadc.c

532

#define VADC_NO_CHAN(_dname, _type, _mask, _pre) \

drivers/iio/adc/qcom-spmi-vadc.c

537

.info_mask = _mask \

drivers/iio/addac/ad74115.c

245

#define AD74115_FW_PROP(_name, _max, _reg, _mask) \

drivers/iio/addac/ad74115.c

250

.mask = (_mask), \

drivers/iio/addac/ad74115.c

253

#define AD74115_FW_PROP_TBL(_name, _tbl, _reg, _mask) \

drivers/iio/addac/ad74115.c

257

.mask = (_mask), \

drivers/iio/addac/ad74115.c

262

#define AD74115_FW_PROP_BOOL(_name, _reg, _mask) \

drivers/iio/addac/ad74115.c

267

.mask = (_mask), \

drivers/iio/addac/ad74115.c

270

#define AD74115_FW_PROP_BOOL_NEG(_name, _reg, _mask) \

drivers/iio/addac/ad74115.c

276

.mask = (_mask), \

drivers/iio/health/afe440x.h

83

#define AFE440X_INTENSITY_CHAN(_index, _mask) \

drivers/iio/health/afe440x.h

96

_mask, \

drivers/iio/light/opt4060.c

526

#define _OPT4060_COLOR_CHANNEL(_color, _mask, _ev_spec, _num_ev_spec) \

drivers/iio/light/opt4060.c

531

.info_mask_separate = _mask, \

drivers/iio/light/opt4060.c

546

#define OPT4060_COLOR_CHANNEL(_color, _mask) \

drivers/iio/light/opt4060.c

547

_OPT4060_COLOR_CHANNEL(_color, _mask, opt4060_event_spec, \

drivers/iio/light/opt4060.c

550

#define OPT4060_COLOR_CHANNEL_NO_EVENTS(_color, _mask) \

drivers/iio/light/opt4060.c

551

_OPT4060_COLOR_CHANNEL(_color, _mask, NULL, 0) \

drivers/infiniband/hw/efa/efa_verbs.c

1928

#define EFA_CHECK_USER_COMP(_dev, _comp_mask, _attr, _mask, _attr_str) \

drivers/infiniband/hw/efa/efa_verbs.c

1929

(_attr_str = (!(_dev)->dev_attr._attr || ((_comp_mask) & (_mask))) ? \

drivers/input/mouse/trackpoint.c

172

#define TRACKPOINT_BIT_ATTR(_name, _command, _mask, _inv, _default) \

drivers/input/mouse/trackpoint.c

177

.mask = _mask, \

drivers/iommu/intel/cache.c

259

unsigned long *_mask)

drivers/iommu/intel/cache.c

288

*_mask = mask;

drivers/irqchip/irq-pic32-evic.c

118

#define IRQ_REG_MASK(_hwirq, _reg, _mask) \

drivers/irqchip/irq-pic32-evic.c

121

_mask = 1 << (_hwirq % 32); \

drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h

52

#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask) \

drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h

54

typeof(_mask) (_m) = (_mask); \

drivers/media/rc/rc-main.c

1084

#define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \

drivers/media/rc/rc-main.c

1088

.mask = (_mask), \

drivers/mfd/axp20x.c

486

#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \

drivers/mfd/axp20x.c

487

[_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }

drivers/mfd/max8997-irq.c

54

#define DECLARE_IRQ(idx, _group, _mask) \

drivers/mfd/max8997-irq.c

55

[(idx)] = { .group = (_group), .mask = (_mask) }

drivers/mfd/qcom-pm8008.c

70

#define _IRQ(_irq, _off, _mask, _types) \

drivers/mfd/qcom-pm8008.c

73

.mask = (_mask), \

drivers/mfd/rohm-bd71828.c

24

#define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \

drivers/mfd/rohm-bd71828.c

27

.mask = (_mask), \

drivers/mfd/tps6586x.c

61

#define TPS6586X_IRQ(_reg, _mask) \

drivers/mfd/tps6586x.c

64

.mask_mask = (_mask), \

drivers/mfd/wcd934x.c

19

#define WCD934X_REGMAP_IRQ_REG(_irq, _off, _mask) \

drivers/mfd/wcd934x.c

22

.mask = (_mask), \

drivers/mfd/wcd934x.c

26

.type_reg_mask = (_mask), \

drivers/mfd/wcd934x.c

27

.type_level_low_val = (_mask), \

drivers/mfd/wcd934x.c

28

.type_level_high_val = (_mask), \

drivers/misc/bcm-vk/bcm_vk.h

427

#define BCM_VK_EXTRACT_FIELD(_field, _reg, _mask, _shift) \

drivers/misc/bcm-vk/bcm_vk.h

428

(_field = (((_reg) >> (_shift)) & (_mask)))

drivers/net/dsa/bcm_sf2.h

172

priv->irq##which##_mask &= ~(mask); \

drivers/net/dsa/bcm_sf2.h

179

priv->irq##which##_mask |= (mask); \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1686

#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1687

(XMDIO_READ((_pdata), _mmd, _reg) & _mask)

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1693

#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \

drivers/net/ethernet/amd/xgbe/xgbe-common.h

1696

mmd_val &= ~_mask; \

drivers/net/ethernet/broadcom/bcmsysport.c

66

priv->irq##which##_mask &= ~(mask); \

drivers/net/ethernet/broadcom/bcmsysport.c

73

priv->irq##which##_mask |= (mask); \

drivers/net/ethernet/intel/ice/ice_flow.c

56

#define ICE_FLOW_FLD_INFO_MSK(_hdr, _offset_bytes, _size_bytes, _mask) { \

drivers/net/ethernet/intel/ice/ice_flow.c

60

.mask = _mask, \

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

3293

#define RVU_DBG_PRINT_MPLS_LBTCBOS(_pkt, _mask) \

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

3296

typeof(_mask) (mask) = (_mask); \

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

29

#define DUMP_REG_MASK(_reg, _mask) \

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

30

{ #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }

drivers/net/ethernet/mediatek/mtk_wed_debugfs.c

38

#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

53

struct mlx5dr_match_misc2 *_mask = mask; \

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

55

DR_STE_SET_TAG(lookup_type, _tag, mpls0_label, _mask, \

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

57

DR_STE_SET_TAG(lookup_type, _tag, mpls0_s_bos, _mask, \

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

59

DR_STE_SET_TAG(lookup_type, _tag, mpls0_exp, _mask, \

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

61

DR_STE_SET_TAG(lookup_type, _tag, mpls0_ttl, _mask, \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

532

#define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

536

.mask = _mask, \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

541

#define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

543

_offset, _mask, _shift, _field)

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

545

#define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

547

_offset, _mask, _shift, _field)

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

549

#define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

550

MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_TCP, _offset, _mask, _shift, _field)

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

552

#define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \

drivers/net/ethernet/mellanox/mlxsw/spectrum_acl.c

553

MLXSW_SP_ACL_MANGLE_ACTION(FLOW_ACT_MANGLE_HDR_TYPE_UDP, _offset, _mask, _shift, _field)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

71

#define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

72

#define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))

drivers/net/ethernet/sfc/enum.h

117

#define LOOPBACK_CHANGED(_from, _to, _mask) \

drivers/net/ethernet/sfc/enum.h

118

(!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask)))

drivers/net/ethernet/sfc/enum.h

120

#define LOOPBACK_OUT_OF(_from, _to, _mask) \

drivers/net/ethernet/sfc/enum.h

121

((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask)))

drivers/net/ethernet/sfc/falcon/enum.h

117

#define LOOPBACK_CHANGED(_from, _to, _mask) \

drivers/net/ethernet/sfc/falcon/enum.h

118

(!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask)))

drivers/net/ethernet/sfc/falcon/enum.h

120

#define LOOPBACK_OUT_OF(_from, _to, _mask) \

drivers/net/ethernet/sfc/falcon/enum.h

121

((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask)))

drivers/net/ethernet/sfc/siena/enum.h

117

#define LOOPBACK_CHANGED(_from, _to, _mask) \

drivers/net/ethernet/sfc/siena/enum.h

118

(!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask)))

drivers/net/ethernet/sfc/siena/enum.h

120

#define LOOPBACK_OUT_OF(_from, _to, _mask) \

drivers/net/ethernet/sfc/siena/enum.h

121

((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask)))

drivers/net/wireless/ath/ath5k/ath5k.h

128

#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \

drivers/net/wireless/ath/ath5k/ath5k.h

130

(_mask)) | (_flags), _reg)

drivers/net/wireless/realtek/rtw89/phy.h

790

#define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \

drivers/net/wireless/realtek/rtw89/phy.h

794

.mask = _mask, \

drivers/net/wireless/realtek/rtw89/phy.h

797

#define RTW89_DECL_RFK_WM(_addr, _mask, _data) \

drivers/net/wireless/realtek/rtw89/phy.h

800

.mask = _mask, \

drivers/net/wireless/realtek/rtw89/phy.h

803

#define RTW89_DECL_RFK_WS(_addr, _mask) \

drivers/net/wireless/realtek/rtw89/phy.h

806

.mask = _mask,}

drivers/net/wireless/realtek/rtw89/phy.h

808

#define RTW89_DECL_RFK_WC(_addr, _mask) \

drivers/net/wireless/realtek/rtw89/phy.h

811

.mask = _mask,}

drivers/perf/arm-ccn.c

277

#define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \

drivers/perf/arm-ccn.c

280

.def = _def, .mask = _mask, }

drivers/perf/arm-ccn.c

282

#define CCN_EVENT_HNI(_name, _def, _mask) { \

drivers/perf/arm-ccn.c

285

.num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }

drivers/perf/arm-ccn.c

287

#define CCN_EVENT_SBSX(_name, _def, _mask) { \

drivers/perf/arm-ccn.c

290

.num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }

drivers/phy/microchip/lan966x_serdes.c

29

#define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \

drivers/phy/microchip/lan966x_serdes.c

34

.mask = _mask, \

drivers/phy/mscc/phy-ocelot-serdes.c

345

#define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \

drivers/phy/mscc/phy-ocelot-serdes.c

350

.mask = _mask, \

drivers/phy/tegra/xusb-tegra124.c

404

#define TEGRA124_LANE(_name, _offset, _shift, _mask, _type) \

drivers/phy/tegra/xusb-tegra124.c

409

.mask = _mask, \

drivers/phy/tegra/xusb-tegra186.c

243

#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \

drivers/phy/tegra/xusb-tegra186.c

248

.mask = _mask, \

drivers/phy/tegra/xusb-tegra210.c

1732

#define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \

drivers/phy/tegra/xusb-tegra210.c

1737

.mask = _mask, \

drivers/phy/tegra/xusb-tegra210.c

2534

#define TEGRA210_UPHY_LANE(_name, _offset, _shift, _mask, _type, _misc) \

drivers/phy/tegra/xusb-tegra210.c

2539

.mask = _mask, \

drivers/pinctrl/mediatek/pinctrl-mtmips.h

12

#define GRP(_name, _func, _mask, _shift) \

drivers/pinctrl/mediatek/pinctrl-mtmips.h

13

{ .name = _name, .mask = _mask, .shift = _shift, \

drivers/pinctrl/mediatek/pinctrl-mtmips.h

14

.func = _func, .gpio = _mask, \

drivers/pinctrl/mediatek/pinctrl-mtmips.h

17

#define GRP_G(_name, _func, _mask, _gpio, _shift) \

drivers/pinctrl/mediatek/pinctrl-mtmips.h

18

{ .name = _name, .mask = _mask, .shift = _shift, \

drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c

76

#define MPFS_IOMUX0_GROUP(_name, _mask) { \

drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c

79

.mask = _mask, \

drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c

84

.mask = _mask, \

drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c

85

.setting = _mask, \

drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c

122

#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \

drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c

126

.mask = _mask, \

drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c

132

.mask = _mask, \

drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c

133

.setting = _mask, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

123

#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

128

.reg_mask = _mask, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

129

.val = {0, _mask}, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

133

#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

138

.reg_mask = _mask, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

143

#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

148

.reg_mask = _mask, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

153

#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c

159

.reg_mask = _mask, \

drivers/pinctrl/mvebu/pinctrl-mvebu.h

157

#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \

drivers/pinctrl/mvebu/pinctrl-mvebu.h

162

.variant = _mask, \

drivers/pinctrl/mvebu/pinctrl-mvebu.h

167

#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \

drivers/pinctrl/mvebu/pinctrl-mvebu.h

168

_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)

drivers/pinctrl/mvebu/pinctrl-mvebu.h

170

#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \

drivers/pinctrl/mvebu/pinctrl-mvebu.h

171

_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)

drivers/pinctrl/pinctrl-ep93xx.c

60

#define PMX_GROUP(_name, _pins, _mask, _value) \

drivers/pinctrl/pinctrl-ep93xx.c

63

.mask = _mask, \

drivers/pinctrl/pinctrl-palmas.c

378

#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \

drivers/pinctrl/pinctrl-palmas.c

382

.pullup_dn_mask = _mask, \

drivers/pinctrl/pinctrl-palmas.c

414

#define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \

drivers/pinctrl/pinctrl-palmas.c

418

.od_mask = _mask, \

drivers/pinctrl/pinctrl-palmas.c

492

#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \

drivers/pinctrl/pinctrl-palmas.c

499

.mux_reg_mask = _mask, \

drivers/pinctrl/pinctrl-pef2256.c

179

#define PEF2256_PINCTRL_PIN(_number, _name, _offset, _mask) { \

drivers/pinctrl/pinctrl-pef2256.c

184

.mask = _mask, \

drivers/pinctrl/pinctrl-pistachio.c

500

#define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \

drivers/pinctrl/pinctrl-pistachio.c

509

.scenario_mask = _mask, \

drivers/pinctrl/pinctrl-pistachio.c

663

#define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \

drivers/pinctrl/pinctrl-pistachio.c

674

.mux_mask = _mask, \

drivers/pinctrl/spear/pinctrl-plgpio.c

667

#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \

drivers/pinctrl/spear/pinctrl-plgpio.c

670

_tmp &= ~_mask; \

drivers/pinctrl/spear/pinctrl-plgpio.c

672

_tmp | (plgpio->csave_regs[i].__reg & _mask); \

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

703

u16 _mask, u16 _value)

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

707

u32 mask = (u32)_mask << shift;

drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c

711

dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

823

#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c

828

.mask = _mask, \

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1007

u64 val, _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1012

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1013

val &= _mask; \

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

789

u64 val, _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

793

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

794

val &= _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

801

u64 val, _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

805

_mask = GENMASK((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

806

val &= ~_mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

814

u64 val, _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

819

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

820

val &= _mask; \

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

827

u64 val, _mask;\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

832

_mask = GENMASK_ULL((start + width - 1), start);\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

833

val &= _mask; \

drivers/pmdomain/mediatek/mt8365-pm-domains.h

13

#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \

drivers/pmdomain/mediatek/mt8365-pm-domains.h

14

BUS_PROT_WR(INFRA, _mask, \

drivers/pmdomain/mediatek/mt8365-pm-domains.h

19

#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \

drivers/pmdomain/mediatek/mt8365-pm-domains.h

20

BUS_PROT_WR(INFRA, _mask, \

drivers/pmdomain/mediatek/mtk-pm-domains.h

87

#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \

drivers/pmdomain/mediatek/mtk-pm-domains.h

88

_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, 0)

drivers/pmdomain/mediatek/mtk-pm-domains.h

90

#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \

drivers/pmdomain/mediatek/mtk-pm-domains.h

91

_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \

drivers/pmdomain/mediatek/mtk-pm-domains.h

94

#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \

drivers/pmdomain/mediatek/mtk-pm-domains.h

95

_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \

drivers/pmdomain/mediatek/mtk-pm-domains.h

98

#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \

drivers/pmdomain/mediatek/mtk-pm-domains.h

99

BUS_PROT_UPDATE(INFRA, _mask, \

drivers/regulator/ab8500.c

1158

#define REG_INIT(_id, _bank, _addr, _mask) \

drivers/regulator/ab8500.c

1162

.mask = _mask, \

drivers/regulator/da9063-regulator.c

26

#define BFIELD(_reg, _mask) \

drivers/regulator/da9063-regulator.c

27

REG_FIELD(_reg, __builtin_ffs((int)_mask) - 1, \

drivers/regulator/da9063-regulator.c

28

sizeof(unsigned int) * 8 - __builtin_clz((_mask)) - 1)

drivers/regulator/max8997-regulator.c

287

int *_reg, int *_shift, int *_mask)

drivers/regulator/max8997-regulator.c

347

*_mask = mask;

drivers/regulator/max8998.c

134

int *_reg, int *_shift, int *_mask)

drivers/regulator/max8998.c

191

*_mask = mask;

drivers/regulator/max8998.c

491

#define MAX8998_CURRENT_REG(_name, _ops, _table, _reg, _mask) \

drivers/regulator/max8998.c

499

.csel_mask = _mask, \

drivers/regulator/spacemit-p1.c

71

#define P1_REG_DESC(_TYPE, _type, _n, _s, _off, _mask, _nv, _ranges) \

drivers/regulator/spacemit-p1.c

84

.vsel_mask = _mask, \

drivers/regulator/tps6524x-regulator.c

371

#define __MK_FIELD(_reg, _mask, _shift) \

drivers/regulator/tps6524x-regulator.c

372

{ .reg = (_reg), .mask = (_mask), .shift = (_shift), }

drivers/ssb/pci.c

171

#define SPEX16(_outvar, _offset, _mask, _shift) \

drivers/ssb/pci.c

172

out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))

drivers/ssb/pci.c

173

#define SPEX32(_outvar, _offset, _mask, _shift) \

drivers/ssb/pci.c

175

in[SPOFF(_offset)]) & (_mask)) >> (_shift))

drivers/ssb/pci.c

176

#define SPEX(_outvar, _offset, _mask, _shift) \

drivers/ssb/pci.c

177

SPEX16(_outvar, _offset, _mask, _shift)

drivers/ssb/pci.c

179

#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \

drivers/ssb/pci.c

181

SPEX(_field[0], _offset + 0, _mask, _shift); \

drivers/ssb/pci.c

182

SPEX(_field[1], _offset + 2, _mask, _shift); \

drivers/ssb/pci.c

183

SPEX(_field[2], _offset + 4, _mask, _shift); \

drivers/ssb/pci.c

184

SPEX(_field[3], _offset + 6, _mask, _shift); \

drivers/ssb/pci.c

185

SPEX(_field[4], _offset + 8, _mask, _shift); \

drivers/ssb/pci.c

186

SPEX(_field[5], _offset + 10, _mask, _shift); \

drivers/ssb/pci.c

187

SPEX(_field[6], _offset + 12, _mask, _shift); \

drivers/ssb/pci.c

188

SPEX(_field[7], _offset + 14, _mask, _shift); \

drivers/usb/typec/tipd/tps6598x.h

15

#define TPS_FIELD_GET(_mask, _reg) ((typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)))

include/linux/bitfield.h

108

#define FIELD_MAX(_mask) \

include/linux/bitfield.h

110

__BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \

include/linux/bitfield.h

111

(typeof(_mask))((_mask) >> __bf_shf(_mask)); \

include/linux/bitfield.h

121

#define FIELD_FIT(_mask, _val) \

include/linux/bitfield.h

123

__BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \

include/linux/bitfield.h

124

!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \

include/linux/bitfield.h

135

#define FIELD_PREP(_mask, _val) \

include/linux/bitfield.h

137

__BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \

include/linux/bitfield.h

138

__FIELD_PREP(_mask, _val, "FIELD_PREP: "); \

include/linux/bitfield.h

155

#define FIELD_PREP_CONST(_mask, _val) \

include/linux/bitfield.h

158

BUILD_BUG_ON_ZERO((_mask) == 0) + \

include/linux/bitfield.h

160

BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \

include/linux/bitfield.h

162

__BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + \

include/linux/bitfield.h

164

(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) \

include/linux/bitfield.h

175

#define FIELD_GET(_mask, _reg) \

include/linux/bitfield.h

177

__BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \

include/linux/bitfield.h

178

__FIELD_GET(_mask, _reg, "FIELD_GET: "); \

include/linux/bitfield.h

190

#define FIELD_MODIFY(_mask, _reg_p, _val) \

include/linux/bitfield.h

193

__BF_FIELD_CHECK(_mask, *(_reg_p), _val, "FIELD_MODIFY: "); \

include/linux/bitfield.h

194

*(_reg_p) &= ~(_mask); \

include/linux/bitfield.h

195

*(_reg_p) |= (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)); \

include/linux/bitfield.h

65

#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \

include/linux/bitfield.h

67

BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \

include/linux/bitfield.h

69

BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \

include/linux/bitfield.h

71

~((_mask) >> __bf_shf(_mask)) & \

include/linux/bitfield.h

74

__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \

include/linux/bitfield.h

75

(1ULL << __bf_shf(_mask))); \

include/linux/hw_bitfield.h

26

#define FIELD_PREP_WM16(_mask, _val) \

include/linux/hw_bitfield.h

29

typeof(_mask) __mask = _mask; \

include/linux/hw_bitfield.h

54

#define FIELD_PREP_WM16_CONST(_mask, _val) \

include/linux/hw_bitfield.h

56

FIELD_PREP_CONST(_mask, _val) | \

include/linux/hw_bitfield.h

57

(BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \

include/linux/hw_bitfield.h

58

((_mask) << 16)) \

include/linux/netfilter/x_tables.h

395

const char *_mask)

include/linux/netfilter/x_tables.h

399

const unsigned long *mask = (const unsigned long *)_mask;

include/linux/nospec.h

59

unsigned long _mask = array_index_mask_nospec(_i, _s); \

include/linux/nospec.h

64

(typeof(_i)) (_i & _mask); \

include/linux/perf/arm_pmu.h

155

#define PMU_PROBE(_cpuid, _mask, _fn) \

include/linux/perf/arm_pmu.h

158

.mask = (_mask), \

include/linux/regmap.h

1596

#define REGMAP_IRQ_REG(_irq, _off, _mask) \

include/linux/regmap.h

1597

[_irq] = { .reg_offset = (_off), .mask = (_mask) }

include/linux/soc/mediatek/mtk_wed.h

276

#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)

include/linux/soc/mediatek/mtk_wed.h

285

#define mtk_wed_device_irq_get(_dev, _mask) \

include/linux/soc/mediatek/mtk_wed.h

286

(_dev)->ops->irq_get(_dev, _mask)

include/linux/soc/mediatek/mtk_wed.h

287

#define mtk_wed_device_irq_set_mask(_dev, _mask) \

include/linux/soc/mediatek/mtk_wed.h

288

(_dev)->ops->irq_set_mask(_dev, _mask)

include/linux/soc/mediatek/mtk_wed.h

299

#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) \

include/linux/soc/mediatek/mtk_wed.h

300

(_dev)->ops->start_hw_rro(_dev, _mask, _reset)

include/linux/soc/mediatek/mtk_wed.h

314

#define mtk_wed_device_start(_dev, _mask) do {} while (0)

include/linux/soc/mediatek/mtk_wed.h

319

#define mtk_wed_device_irq_get(_dev, _mask) 0

include/linux/soc/mediatek/mtk_wed.h

320

#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)

include/linux/soc/mediatek/mtk_wed.h

327

#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) do {} while (0)

include/net/netlink.h

462

#define NLA_POLICY_MASK(tp, _mask) { \

include/net/netlink.h

465

.mask = _mask, \

include/soc/fsl/qman.h

877

((np)->field & (qm_mcr_##field##_mask))

include/xen/interface/io/ring.h

357

static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \

include/xen/interface/io/ring.h

366

return buf + name##_mask(idx, ring_size); \

include/xen/interface/io/ring.h

384

*masked_cons = name##_mask(*masked_cons + size, ring_size); \

include/xen/interface/io/ring.h

402

*masked_prod = name##_mask(*masked_prod + size, ring_size); \

include/xen/interface/io/ring.h

414

prod = name##_mask(prod, ring_size); \

include/xen/interface/io/ring.h

415

cons = name##_mask(cons, ring_size); \

kernel/events/core.c

7738

DECLARE_BITMAP(_mask, 64);

kernel/events/core.c

7740

bitmap_from_u64(_mask, mask);

kernel/events/core.c

7741

for_each_set_bit(bit, _mask, sizeof(mask) * BITS_PER_BYTE) {

kernel/sched/core.c

965

typeof(mask) _mask = (mask); \

kernel/sched/core.c

969

} while (!try_cmpxchg(_ptr, &_val, _val | _mask)); \

lib/tests/cpumask_kunit.c

55

KUNIT_EXPECT_EQ_MSG((test), mask_weight, iter, MASK_MSG(cpu_##name##_mask)); \

net/bridge/br_sysfs_if.c

47

#define BRPORT_ATTR_FLAG(_name, _mask) \

net/bridge/br_sysfs_if.c

50

return sysfs_emit(buf, "%d\n", !!(p->flags & _mask)); \

net/bridge/br_sysfs_if.c

54

return store_flag(p, v, _mask); \

net/ipv4/netfilter/arp_tables.c

64

static unsigned long ifname_compare(const char *_a, const char *_b, const char *_mask)

net/ipv4/netfilter/arp_tables.c

67

unsigned long ret = ifname_compare_aligned(_a, _b, _mask);

net/ipv4/netfilter/arp_tables.c

72

const u16 *mask = (const u16 *)_mask;

net/sched/cls_flower.c

3113

__be32 _key, _mask;

net/sched/cls_flower.c

3153

_mask = cpu_to_be32(mask);

net/sched/cls_flower.c

3159

return nla_put(skb, fl_mask, 4, &_mask);

sound/hda/codecs/realtek/realtek.h

159

#define UPDATE_COEFEX(_nid, _idx, _mask, _val) \

sound/hda/codecs/realtek/realtek.h

160

{ .nid = (_nid), .idx = (_idx), .mask = (_mask), .val = (_val) }

sound/hda/codecs/realtek/realtek.h

163

#define UPDATE_COEF(_idx, _mask, _val) UPDATE_COEFEX(0x20, _idx, _mask, _val)

tools/include/linux/bitfield.h

110

#define FIELD_PREP(_mask, _val) \

tools/include/linux/bitfield.h

112

__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \

tools/include/linux/bitfield.h

113

((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \

tools/include/linux/bitfield.h

124

#define FIELD_GET(_mask, _reg) \

tools/include/linux/bitfield.h

126

__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \

tools/include/linux/bitfield.h

127

(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \

tools/include/linux/bitfield.h

61

#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \

tools/include/linux/bitfield.h

63

BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \

tools/include/linux/bitfield.h

65

BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \

tools/include/linux/bitfield.h

67

~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \

tools/include/linux/bitfield.h

69

BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \

tools/include/linux/bitfield.h

72

__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \

tools/include/linux/bitfield.h

73

(1ULL << __bf_shf(_mask))); \

tools/include/linux/bitfield.h

83

#define FIELD_MAX(_mask) \

tools/include/linux/bitfield.h

85

__BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \

tools/include/linux/bitfield.h

86

(typeof(_mask))((_mask) >> __bf_shf(_mask)); \

tools/include/linux/bitfield.h

96

#define FIELD_FIT(_mask, _val) \

tools/include/linux/bitfield.h

98

__BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \

tools/include/linux/bitfield.h

99

!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

429

& REG##_mask)

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

431

& REG##_mask)

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

437

#define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

441

#define ungetp32(ST, REG) (getp32(ST, REG) & ~((REG##_mask) \

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

453

& REG##_mask) << (31-REG##_offset))))

tools/testing/selftests/powerpc/nx-gzip/include/nxu.h

455

| (((X) & REG##_mask) << (31-REG##_offset))))