arch/powerpc/include/asm/perf_event_server.h
171
#define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
arch/powerpc/include/asm/perf_event_server.h
172
#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
arch/powerpc/include/asm/perf_event_server.h
174
#define EVENT_ATTR(_name, _id, _suffix) \
arch/powerpc/include/asm/perf_event_server.h
175
PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \
arch/powerpc/include/asm/perf_event_server.h
178
#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
arch/powerpc/include/asm/perf_event_server.h
179
#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
arch/powerpc/include/asm/perf_event_server.h
181
#define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c)
arch/powerpc/include/asm/perf_event_server.h
182
#define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c)
arch/powerpc/include/asm/perf_event_server.h
184
#define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p)
arch/powerpc/include/asm/perf_event_server.h
185
#define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p)
arch/powerpc/perf/kvm-hv-pmu.c
41
#define KVMPPC_PMU_EVENT_ATTR(_name, _id) \
arch/powerpc/perf/kvm-hv-pmu.c
42
PMU_EVENT_ATTR_ID(_name, kvmppc_events_sysfs_show, _id)
arch/powerpc/perf/vpa-pmu.c
19
#define VPA_PMU_EVENT_VAR(_id) event_attr_##_id
arch/powerpc/perf/vpa-pmu.c
20
#define VPA_PMU_EVENT_PTR(_id) (&event_attr_##_id.attr.attr)
arch/powerpc/perf/vpa-pmu.c
32
#define VPA_PMU_EVENT_ATTR(_name, _id) \
arch/powerpc/perf/vpa-pmu.c
33
PMU_EVENT_ATTR(_name, VPA_PMU_EVENT_VAR(_id), _id, \
arch/riscv/include/asm/cpufeature.h
43
#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \
arch/riscv/include/asm/cpufeature.h
46
.id = _id, \
arch/riscv/include/asm/cpufeature.h
52
#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL)
arch/riscv/include/asm/cpufeature.h
54
#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \
arch/riscv/include/asm/cpufeature.h
55
_RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate)
arch/riscv/include/asm/cpufeature.h
66
#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
arch/riscv/include/asm/cpufeature.h
67
_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), NULL)
arch/riscv/include/asm/cpufeature.h
68
#define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \
arch/riscv/include/asm/cpufeature.h
69
_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate)
arch/s390/include/asm/debug.h
256
#define debug_sprintf_event(_id, _level, _fmt, ...) \
arch/s390/include/asm/debug.h
259
debug_info_t *__id = _id; \
arch/s390/include/asm/debug.h
386
#define debug_sprintf_exception(_id, _level, _fmt, ...) \
arch/s390/include/asm/debug.h
389
debug_info_t *__id = _id; \
arch/x86/events/perf_event.h
1115
#define EVENT_VAR(_id) event_attr_##_id
arch/x86/events/perf_event.h
1116
#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
arch/x86/events/perf_event.h
1118
#define EVENT_ATTR(_name, _id) \
arch/x86/events/perf_event.h
1119
static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
arch/x86/events/perf_event.h
1121
.id = PERF_COUNT_HW_##_id, \
arch/x86/events/perf_event.h
1148
#define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
arch/x86/kernel/cpu/resctrl/intel_aet.c
51
#define EVT(_id, _idx, _bits) { .id = _id, .idx = _idx, .bin_bits = _bits }
drivers/android/binder.c
176
#define binder_set_extended_error(ee, _id, _command, _param) \
drivers/android/binder.c
178
(ee)->id = _id; \
drivers/clk/aspeed/clk-ast2700.c
276
#define FIXED_CLK(_id, _name, _rate) \
drivers/clk/aspeed/clk-ast2700.c
278
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
284
#define FIXED_DISPLAY_CLK(_id, _name, _reg) \
drivers/clk/aspeed/clk-ast2700.c
286
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
292
#define PLL_CLK(_id, _type, _name, _parent_id, _reg) \
drivers/clk/aspeed/clk-ast2700.c
294
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
303
#define MUX_CLK(_id, _name, _parent_ids, _num_parents, _parent_hws, _reg, _shift, _width) \
drivers/clk/aspeed/clk-ast2700.c
305
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
320
#define DIVIDER_CLK(_id, _name, _parent_id, _reg, _shift, _width, _div_table) \
drivers/clk/aspeed/clk-ast2700.c
322
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
336
#define FIXED_FACTOR_CLK(_id, _name, _parent_id, _mult, _div) \
drivers/clk/aspeed/clk-ast2700.c
338
.id = _id, \
drivers/clk/aspeed/clk-ast2700.c
344
#define GATE_CLK(_id, _type, _name, _parent_id, _reg, _bit, _flags) \
drivers/clk/aspeed/clk-ast2700.c
346
.id = _id, \
drivers/clk/at91/sama7d65.c
436
#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp}
drivers/clk/at91/sama7g5.c
347
#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp}
drivers/clk/baikal-t1/clk-ccu-div.c
57
#define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
drivers/clk/baikal-t1/clk-ccu-div.c
59
.id = _id, \
drivers/clk/baikal-t1/clk-ccu-div.c
69
#define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
drivers/clk/baikal-t1/clk-ccu-div.c
71
.id = _id, \
drivers/clk/baikal-t1/clk-ccu-div.c
79
#define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags) \
drivers/clk/baikal-t1/clk-ccu-div.c
81
.id = _id, \
drivers/clk/baikal-t1/clk-ccu-div.c
89
#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
drivers/clk/baikal-t1/clk-ccu-div.c
91
.id = _id, \
drivers/clk/baikal-t1/clk-ccu-pll.c
35
#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags, _features) \
drivers/clk/baikal-t1/clk-ccu-pll.c
37
.id = _id, \
drivers/clk/clk-bm1880.c
143
#define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
drivers/clk/clk-bm1880.c
146
.id = _id, \
drivers/clk/clk-bm1880.c
160
#define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \
drivers/clk/clk-bm1880.c
162
.id = _id, \
drivers/clk/clk-bm1880.c
174
#define CLK_PLL(_id, _name, _parent, _reg, _flags) { \
drivers/clk/clk-bm1880.c
175
.pll.id = _id, \
drivers/clk/clk-bm1880.c
183
#define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \
drivers/clk/clk-bm1880.c
185
.div.id = _id, \
drivers/clk/clk-loongson2.c
109
#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
drivers/clk/clk-loongson2.c
111
.id = _id, \
drivers/clk/clk-loongson2.c
119
#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \
drivers/clk/clk-loongson2.c
122
.id = _id, \
drivers/clk/clk-loongson2.c
131
#define CLK_FIXED(_id, _name, _pname, _rate) \
drivers/clk/clk-loongson2.c
133
.id = _id, \
drivers/clk/clk-loongson2.c
59
#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
drivers/clk/clk-loongson2.c
61
.id = _id, \
drivers/clk/clk-loongson2.c
70
#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
drivers/clk/clk-loongson2.c
73
.id = _id, \
drivers/clk/clk-loongson2.c
84
#define CLK_SCALE(_id, _name, _pname, _offset, \
drivers/clk/clk-loongson2.c
87
.id = _id, \
drivers/clk/clk-loongson2.c
96
#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \
drivers/clk/clk-loongson2.c
99
.id = _id, \
drivers/clk/hisilicon/clk-hi3660-stub.c
27
#define DEFINE_CLK_STUB(_id, _cmd, _name) \
drivers/clk/hisilicon/clk-hi3660-stub.c
29
.id = (_id), \
drivers/clk/mediatek/clk-gate.h
42
#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
drivers/clk/mediatek/clk-gate.h
44
.id = _id, \
drivers/clk/mediatek/clk-gate.h
53
#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
drivers/clk/mediatek/clk-gate.h
54
GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
drivers/clk/mediatek/clk-mt2701-aud.c
18
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-aud.c
19
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2701-aud.c
21
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-aud.c
22
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2701-aud.c
24
#define GATE_AUDIO2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-aud.c
25
GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2701-aud.c
27
#define GATE_AUDIO3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-aud.c
28
GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2701-bdp.c
27
#define GATE_BDP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-bdp.c
28
GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2701-bdp.c
30
#define GATE_BDP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-bdp.c
31
GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2701-eth.c
19
#define GATE_ETH(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-eth.c
20
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt2701-g3d.c
17
#define GATE_G3D(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-g3d.c
18
GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701-hif.c
19
#define GATE_HIF(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-hif.c
20
GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt2701-img.c
21
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-img.c
22
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701-mm.c
27
#define GATE_DISP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-mm.c
28
GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701-mm.c
30
#define GATE_DISP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-mm.c
31
GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701-vdec.c
27
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-vdec.c
28
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2701-vdec.c
30
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701-vdec.c
31
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2701.c
637
#define GATE_TOP_AUD(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701.c
638
GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2701.c
698
#define GATE_ICG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701.c
699
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701.c
817
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701.c
818
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701.c
820
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2701.c
821
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2701.c
921
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
drivers/clk/mediatek/clk-mt2701.c
923
.id = _id, \
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
21
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
25
.id = _id, \
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
44
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
47
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt2712-bdp.c
21
#define GATE_BDP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-bdp.c
22
GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2712-img.c
21
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-img.c
22
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2712-jpgdec.c
21
#define GATE_JPGDEC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-jpgdec.c
22
GATE_MTK(_id, _name, _parent, &jpgdec_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2712-mfg.c
21
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-mfg.c
22
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712-mm.c
33
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-mm.c
34
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712-mm.c
36
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-mm.c
37
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712-mm.c
39
#define GATE_MM2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-mm.c
40
GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712-vdec.c
27
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-vdec.c
28
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2712-vdec.c
30
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-vdec.c
31
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2712-venc.c
21
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712-venc.c
22
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt2712.c
815
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
816
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt2712.c
818
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
819
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt2712.c
843
#define GATE_INFRA(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
844
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712.c
874
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
875
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712.c
877
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
878
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt2712.c
880
#define GATE_PERI2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt2712.c
881
GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt6735-apmixedsys.c
47
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \
drivers/clk/mediatek/clk-mt6735-apmixedsys.c
50
.id = _id, \
drivers/clk/mediatek/clk-mt6765-audio.c
27
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-audio.c
28
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt6765-audio.c
30
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-audio.c
31
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt6765-cam.c
21
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-cam.c
22
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765-img.c
21
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-img.c
22
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765-mipi0a.c
21
#define GATE_MIPI0A(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-mipi0a.c
22
GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt6765-mm.c
21
#define GATE_MM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-mm.c
22
GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765-vcodec.c
21
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765-vcodec.c
22
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt6765.c
488
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
489
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt6765.c
491
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
492
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt6765.c
494
#define GATE_TOP2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
495
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt6765.c
546
#define GATE_IFR2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
547
GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765.c
549
#define GATE_IFR3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
550
GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765.c
552
#define GATE_IFR4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
553
GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765.c
555
#define GATE_IFR5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
556
GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6765.c
637
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6765.c
638
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt6765.c
671
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt6765.c
674
.id = _id, \
drivers/clk/mediatek/clk-mt6765.c
695
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt6765.c
699
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt6779-aud.c
29
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-aud.c
30
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-aud.c
32
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-aud.c
33
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-cam.c
21
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-cam.c
22
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-img.c
21
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-img.c
22
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-ipe.c
21
#define GATE_IPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-ipe.c
22
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-mfg.c
22
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-mfg.c
23
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-mm.c
27
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-mm.c
28
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-mm.c
30
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-mm.c
31
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-vdec.c
28
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-vdec.c
29
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-vdec.c
31
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-vdec.c
32
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779-venc.c
22
#define GATE_VENC_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779-venc.c
23
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779.c
1106
#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt6779.c
1107
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
drivers/clk/mediatek/clk-mt6779.c
1110
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779.c
1111
GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt6779.c
1145
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt6779.c
1150
.id = _id, \
drivers/clk/mediatek/clk-mt6779.c
1172
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt6779.c
1177
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt6779.c
867
#define GATE_INFRA0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779.c
868
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779.c
870
#define GATE_INFRA1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779.c
871
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779.c
873
#define GATE_INFRA2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779.c
874
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6779.c
876
#define GATE_INFRA3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6779.c
877
GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
26
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
28
.id = _id, \
drivers/clk/mediatek/clk-mt6795-infracfg.c
16
#define GATE_ICG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-infracfg.c
17
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
drivers/clk/mediatek/clk-mt6795-mfg.c
19
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-mfg.c
20
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6795-mm.c
13
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-mm.c
14
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6795-mm.c
16
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-mm.c
17
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6795-pericfg.c
15
#define GATE_PERI(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-pericfg.c
16
GATE_MTK(_id, _name, _parent, &peri_cg_regs, \
drivers/clk/mediatek/clk-mt6795-topckgen.c
21
#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
drivers/clk/mediatek/clk-mt6795-topckgen.c
22
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
drivers/clk/mediatek/clk-mt6795-topckgen.c
26
#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
drivers/clk/mediatek/clk-mt6795-topckgen.c
27
TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
drivers/clk/mediatek/clk-mt6795-vdecsys.c
13
#define GATE_VDEC(_id, _name, _parent, _regs) \
drivers/clk/mediatek/clk-mt6795-vdecsys.c
14
GATE_MTK(_id, _name, _parent, _regs, 0, \
drivers/clk/mediatek/clk-mt6795-vencsys.c
19
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6795-vencsys.c
20
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt6797-img.c
19
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-img.c
20
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797-mm.c
26
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-mm.c
27
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797-mm.c
29
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-mm.c
30
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797-vdec.c
27
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-vdec.c
28
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt6797-vdec.c
30
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-vdec.c
31
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt6797-venc.c
21
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797-venc.c
22
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt6797.c
424
#define GATE_ICG0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797.c
425
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797.c
427
#define GATE_ICG1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797.c
428
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797.c
430
#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt6797.c
431
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6797.c
434
#define GATE_ICG2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt6797.c
435
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt6797.c
437
#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt6797.c
438
GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt6797.c
599
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt6797.c
602
.id = _id, \
drivers/clk/mediatek/clk-mt6797.c
619
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt6797.c
622
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
20
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
23
.id = _id, \
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
41
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
44
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
54
#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
55
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt7622-aud.c
19
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-aud.c
20
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622-aud.c
22
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-aud.c
23
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622-aud.c
25
#define GATE_AUDIO2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-aud.c
26
GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622-aud.c
28
#define GATE_AUDIO3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-aud.c
29
GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622-eth.c
17
#define GATE_ETH(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-eth.c
18
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7622-eth.c
40
#define GATE_SGMII(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-eth.c
41
GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7622-hif.c
17
#define GATE_PCIE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-hif.c
18
GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7622-hif.c
20
#define GATE_SSUSB(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-hif.c
21
GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7622-infracfg.c
17
#define GATE_INFRA(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622-infracfg.c
18
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7622.c
19
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622.c
20
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622.c
22
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622.c
23
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt7622.c
25
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622.c
26
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7622.c
28
#define GATE_PERI0_AO(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622.c
29
GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt7622.c
32
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7622.c
33
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7629-eth.c
17
#define GATE_ETH(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629-eth.c
18
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7629-eth.c
40
#define GATE_SGMII(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629-eth.c
41
GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7629-hif.c
17
#define GATE_PCIE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629-hif.c
18
GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7629-hif.c
20
#define GATE_SSUSB(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629-hif.c
21
GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7629.c
23
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7629.c
26
.id = _id, \
drivers/clk/mediatek/clk-mt7629.c
44
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7629.c
47
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7629.c
51
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629.c
52
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7629.c
54
#define GATE_INFRA(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629.c
55
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7629.c
57
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629.c
58
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7629.c
60
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7629.c
61
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7981-apmixed.c
25
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7981-apmixed.c
29
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
drivers/clk/mediatek/clk-mt7981-apmixed.c
38
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
drivers/clk/mediatek/clk-mt7981-apmixed.c
40
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7981-eth.c
25
#define GATE_SGMII0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt7981-eth.c
26
.id = _id, \
drivers/clk/mediatek/clk-mt7981-eth.c
47
#define GATE_SGMII1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt7981-eth.c
48
.id = _id, \
drivers/clk/mediatek/clk-mt7981-eth.c
69
#define GATE_ETH(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt7981-eth.c
70
.id = _id, \
drivers/clk/mediatek/clk-mt7981-infracfg.c
101
#define GATE_INFRA0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7981-infracfg.c
103
.id = _id, .name = _name, .parent_name = _parent, \
drivers/clk/mediatek/clk-mt7981-infracfg.c
108
#define GATE_INFRA1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7981-infracfg.c
110
.id = _id, .name = _name, .parent_name = _parent, \
drivers/clk/mediatek/clk-mt7981-infracfg.c
115
#define GATE_INFRA2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7981-infracfg.c
117
.id = _id, .name = _name, .parent_name = _parent, \
drivers/clk/mediatek/clk-mt7986-apmixed.c
23
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7986-apmixed.c
27
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
drivers/clk/mediatek/clk-mt7986-apmixed.c
36
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
drivers/clk/mediatek/clk-mt7986-apmixed.c
38
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt7986-eth.c
23
#define GATE_SGMII0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-eth.c
24
GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7986-eth.c
39
#define GATE_SGMII1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-eth.c
40
GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7986-eth.c
55
#define GATE_ETH(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-eth.c
56
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt7986-infracfg.c
88
#define GATE_INFRA0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-infracfg.c
89
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7986-infracfg.c
91
#define GATE_INFRA1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-infracfg.c
92
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7986-infracfg.c
94
#define GATE_INFRA2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7986-infracfg.c
95
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt7988-apmixed.c
22
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
drivers/clk/mediatek/clk-mt7988-apmixed.c
26
.id = _id, \
drivers/clk/mediatek/clk-mt7988-eth.c
25
#define GATE_ETHDMA(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7988-eth.c
27
.id = _id, \
drivers/clk/mediatek/clk-mt7988-eth.c
58
#define GATE_SGMII(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7988-eth.c
60
.id = _id, \
drivers/clk/mediatek/clk-mt7988-eth.c
94
#define GATE_ETHWARP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7988-eth.c
96
.id = _id, \
drivers/clk/mediatek/clk-mt7988-infracfg.c
128
#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt7988-infracfg.c
129
GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
drivers/clk/mediatek/clk-mt7988-infracfg.c
132
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt7988-infracfg.c
133
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
drivers/clk/mediatek/clk-mt7988-infracfg.c
136
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt7988-infracfg.c
137
GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
drivers/clk/mediatek/clk-mt7988-infracfg.c
140
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt7988-infracfg.c
141
GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
drivers/clk/mediatek/clk-mt7988-infracfg.c
144
#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt7988-infracfg.c
146
#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt7988-infracfg.c
148
#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt7988-infracfg.c
150
#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt7988-xfipll.c
25
#define GATE_XFIPLL(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt7988-xfipll.c
27
.id = _id, \
drivers/clk/mediatek/clk-mt8135-apmixedsys.c
20
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
drivers/clk/mediatek/clk-mt8135-apmixedsys.c
21
.id = _id, \
drivers/clk/mediatek/clk-mt8135.c
405
#define GATE_ICG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8135.c
406
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8135.c
408
#define GATE_ICG_AO(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8135.c
409
GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8135.c
441
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8135.c
442
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8135.c
444
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8135.c
445
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
22
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
25
.id = _id, \
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
42
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
45
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
77
#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
78
.id = _id, \
drivers/clk/mediatek/clk-mt8167-aud.c
24
#define GATE_AUD(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-aud.c
25
GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8167-img.c
24
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-img.c
25
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
24
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
25
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167-mm.c
30
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-mm.c
31
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167-mm.c
33
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-mm.c
34
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167-vdec.c
30
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-vdec.c
31
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8167-vdec.c
33
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167-vdec.c
34
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8167.c
658
#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
drivers/clk/mediatek/clk-mt8167.c
659
.id = _id, \
drivers/clk/mediatek/clk-mt8167.c
724
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
725
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167.c
727
#define GATE_TOP0_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
728
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8167.c
730
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
731
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167.c
733
#define GATE_TOP2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
734
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167.c
736
#define GATE_TOP2_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
737
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8167.c
739
#define GATE_TOP3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
740
GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8167.c
742
#define GATE_TOP4_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
743
GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8167.c
745
#define GATE_TOP5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8167.c
746
GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8173-apmixedsys.c
24
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8173-apmixedsys.c
27
.id = _id, \
drivers/clk/mediatek/clk-mt8173-apmixedsys.c
44
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8173-apmixedsys.c
47
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8173-img.c
20
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-img.c
21
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8173-infracfg.c
16
#define GATE_ICG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-infracfg.c
17
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
drivers/clk/mediatek/clk-mt8173-mm.c
28
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-mm.c
29
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8173-mm.c
31
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-mm.c
32
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8173-pericfg.c
14
#define GATE_PERI0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-pericfg.c
15
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, \
drivers/clk/mediatek/clk-mt8173-pericfg.c
18
#define GATE_PERI1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-pericfg.c
19
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, \
drivers/clk/mediatek/clk-mt8173-topckgen.c
22
#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
drivers/clk/mediatek/clk-mt8173-topckgen.c
23
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
drivers/clk/mediatek/clk-mt8173-topckgen.c
27
#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
drivers/clk/mediatek/clk-mt8173-topckgen.c
28
TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
drivers/clk/mediatek/clk-mt8173-vdecsys.c
14
#define GATE_VDEC(_id, _name, _parent, _regs) \
drivers/clk/mediatek/clk-mt8173-vdecsys.c
15
GATE_MTK(_id, _name, _parent, _regs, 0, \
drivers/clk/mediatek/clk-mt8173-vencsys.c
20
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8173-vencsys.c
21
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
24
#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
25
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
28
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
29
GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
54
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
59
.id = _id, \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
81
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
86
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8183-audio.c
27
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-audio.c
28
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-audio.c
31
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-audio.c
32
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-cam.c
20
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-cam.c
21
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-img.c
20
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-img.c
21
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu0.c
20
#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu0.c
21
GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu1.c
20
#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu1.c
21
GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_adl.c
20
#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_adl.c
21
GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
44
#define GATE_IPU_CONN(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
45
GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
48
#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
49
GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
52
#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
53
GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
56
#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
57
GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
60
#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
61
GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
21
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
22
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-mm.c
26
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-mm.c
27
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-mm.c
30
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-mm.c
31
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-vdec.c
26
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-vdec.c
27
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-vdec.c
30
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-vdec.c
31
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183-venc.c
20
#define GATE_VENC_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183-venc.c
21
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
639
#define GATE_TOP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
640
GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
673
#define GATE_INFRA0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
674
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
677
#define GATE_INFRA1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
678
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
681
#define GATE_INFRA2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
682
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
685
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8183.c
686
GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, \
drivers/clk/mediatek/clk-mt8183.c
689
#define GATE_INFRA3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
690
GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8183.c
693
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8183.c
694
GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, \
drivers/clk/mediatek/clk-mt8183.c
815
#define GATE_PERI(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8183.c
816
GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
19
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
23
.id = _id, \
drivers/clk/mediatek/clk-mt8186-cam.c
19
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-cam.c
20
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-img.c
19
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-img.c
20
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
19
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c
20
GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-infra_ao.c
38
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
39
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
42
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
43
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8186-infra_ao.c
45
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
46
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
49
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
50
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8186-infra_ao.c
52
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
53
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
56
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
57
GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8186-infra_ao.c
59
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
60
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
63
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-infra_ao.c
64
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8186-ipe.c
19
#define GATE_IPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-ipe.c
20
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-mdp.c
25
#define GATE_MDP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-mdp.c
26
GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-mdp.c
28
#define GATE_MDP2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-mdp.c
29
GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-mfg.c
19
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-mfg.c
20
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8186-mm.c
25
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-mm.c
26
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-mm.c
28
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-mm.c
29
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8186-vdec.c
39
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-vdec.c
40
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8186-vdec.c
42
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-vdec.c
43
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8186-vdec.c
45
#define GATE_VDEC2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-vdec.c
46
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8186-vdec.c
48
#define GATE_VDEC3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-vdec.c
49
GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8186-venc.c
19
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-venc.c
20
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8186-wpe.c
19
#define GATE_WPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8186-wpe.c
20
GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
22
#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
23
GATE_MTK(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-apmixedsys.c
21
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-apmixedsys.c
22
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-apmixedsys.c
32
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8188-apmixedsys.c
37
.id = _id, \
drivers/clk/mediatek/clk-mt8188-cam.c
20
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-cam.c
21
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-ccu.c
20
#define GATE_CCU(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-ccu.c
21
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-img.c
20
#define GATE_IMGSYS(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-img.c
21
GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c
22
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c
23
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
45
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
46
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
49
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
50
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8188-infra_ao.c
52
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
53
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
56
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
57
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8188-infra_ao.c
59
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
60
GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-infra_ao.c
62
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
63
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
66
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
67
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
70
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
71
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8188-infra_ao.c
73
#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
74
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
77
#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-infra_ao.c
78
GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8188-ipe.c
20
#define GATE_IPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-ipe.c
21
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-mfg.c
20
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-mfg.c
21
GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-peri_ao.c
20
#define GATE_PERI_AO(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-peri_ao.c
21
GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-topckgen.c
1204
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-topckgen.c
1205
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-topckgen.c
1207
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-topckgen.c
1208
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-vdec.c
32
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdec.c
33
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8188-vdec.c
35
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdec.c
36
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8188-vdec.c
38
#define GATE_VDEC2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdec.c
39
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8188-vdo0.c
34
#define GATE_VDO0_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo0.c
35
GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo0.c
37
#define GATE_VDO0_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo0.c
38
GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo0.c
40
#define GATE_VDO0_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo0.c
41
GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo0.c
43
#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt8188-vdo0.c
44
GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-vdo1.c
52
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
53
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo1.c
55
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
56
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo1.c
58
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
59
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo1.c
61
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
62
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo1.c
64
#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
65
GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8188-vdo1.c
68
#define GATE_VDO1_4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
69
GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vdo1.c
71
#define GATE_VDO1_5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vdo1.c
72
GATE_MTK(_id, _name, _parent, &vdo1_5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-venc.c
22
#define GATE_VENC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-venc.c
23
GATE_MTK(_id, _name, _parent, &venc1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8188-vpp0.c
32
#define GATE_VPP0_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vpp0.c
33
GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vpp0.c
35
#define GATE_VPP0_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vpp0.c
36
GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vpp0.c
38
#define GATE_VPP0_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vpp0.c
39
GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vpp1.c
26
#define GATE_VPP1_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vpp1.c
27
GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-vpp1.c
29
#define GATE_VPP1_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-vpp1.c
30
GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8188-wpe.c
34
#define GATE_WPE_TOP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-wpe.c
35
GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-wpe.c
37
#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-wpe.c
38
GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8188-wpe.c
40
#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8188-wpe.c
41
GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
24
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
25
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
35
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
40
.id = _id, \
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
63
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
67
PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8192-aud.c
33
#define GATE_AUD0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-aud.c
34
GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8192-aud.c
36
#define GATE_AUD1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-aud.c
37
GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8192-aud.c
39
#define GATE_AUD2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-aud.c
40
GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8192-cam.c
21
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-cam.c
22
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-img.c
21
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-img.c
22
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
21
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
22
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8192-ipe.c
21
#define GATE_IPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-ipe.c
22
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-mdp.c
27
#define GATE_MDP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mdp.c
28
GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-mdp.c
30
#define GATE_MDP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mdp.c
31
GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-mfg.c
21
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mfg.c
22
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
drivers/clk/mediatek/clk-mt8192-mm.c
32
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mm.c
33
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-mm.c
35
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mm.c
36
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-mm.c
38
#define GATE_MM2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-mm.c
39
GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192-msdc.c
21
#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-msdc.c
22
GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8192-scp_adsp.c
21
#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-scp_adsp.c
22
GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8192-vdec.c
33
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-vdec.c
34
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8192-vdec.c
36
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-vdec.c
37
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8192-vdec.c
39
#define GATE_VDEC2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-vdec.c
40
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8192-venc.c
21
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192-venc.c
22
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8192.c
749
#define GATE_INFRA0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
750
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192.c
752
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8192.c
753
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8192.c
756
#define GATE_INFRA1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
757
GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8192.c
759
#define GATE_INFRA2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
760
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192.c
762
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8192.c
763
GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8192.c
766
#define GATE_INFRA3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
767
GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8192.c
769
#define GATE_INFRA4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
770
GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8192.c
772
#define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8192.c
773
GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8192.c
776
#define GATE_INFRA5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
777
GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8192.c
921
#define GATE_PERI(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
922
GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8192.c
934
#define GATE_TOP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8192.c
935
GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
22
#define GATE_APMIXED(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
23
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
33
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
38
.id = _id, \
drivers/clk/mediatek/clk-mt8195-apusys_pll.c
28
#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \
drivers/clk/mediatek/clk-mt8195-apusys_pll.c
29
.id = _id, \
drivers/clk/mediatek/clk-mt8195-cam.c
19
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-cam.c
20
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-ccu.c
19
#define GATE_CCU(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-ccu.c
20
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-img.c
19
#define GATE_IMG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-img.c
20
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
19
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
20
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
44
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
45
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
48
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
49
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-infra_ao.c
51
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
52
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
55
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
56
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-infra_ao.c
58
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
59
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
62
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
63
GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-infra_ao.c
65
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
66
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
69
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
70
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-infra_ao.c
72
#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
73
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
76
#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-infra_ao.c
77
GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-ipe.c
19
#define GATE_IPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-ipe.c
20
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8195-mfg.c
19
#define GATE_MFG(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-mfg.c
20
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
drivers/clk/mediatek/clk-mt8195-peri_ao.c
19
#define GATE_PERI_AO(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-peri_ao.c
20
GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-scp_adsp.c
19
#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-scp_adsp.c
20
GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8195-topckgen.c
1198
#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag) \
drivers/clk/mediatek/clk-mt8195-topckgen.c
1199
GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-topckgen.c
1202
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-topckgen.c
1203
GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8195-topckgen.c
1205
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-topckgen.c
1206
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-vdec.c
31
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdec.c
32
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8195-vdec.c
34
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdec.c
35
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8195-vdec.c
37
#define GATE_VDEC2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdec.c
38
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8195-vdo0.c
31
#define GATE_VDO0_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo0.c
32
GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo0.c
34
#define GATE_VDO0_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo0.c
35
GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo0.c
37
#define GATE_VDO0_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo0.c
38
GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo0.c
40
#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt8195-vdo0.c
41
GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-vdo1.c
43
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
44
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo1.c
46
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
47
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo1.c
49
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
50
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo1.c
52
#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
53
GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8195-vdo1.c
56
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
57
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vdo1.c
59
#define GATE_VDO1_4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vdo1.c
60
GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-venc.c
19
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-venc.c
20
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8195-vpp0.c
31
#define GATE_VPP0_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vpp0.c
32
GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vpp0.c
34
#define GATE_VPP0_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vpp0.c
35
GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vpp0.c
37
#define GATE_VPP0_2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vpp0.c
38
GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vpp1.c
25
#define GATE_VPP1_0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vpp1.c
26
GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-vpp1.c
28
#define GATE_VPP1_1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-vpp1.c
29
GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8195-wpe.c
31
#define GATE_WPE(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-wpe.c
32
GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-wpe.c
34
#define GATE_WPE_VPP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-wpe.c
35
GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8195-wpe.c
37
#define GATE_WPE_VPP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8195-wpe.c
38
GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
64
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
68
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp0.c
42
#define GATE_MM0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp0.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp0.c
52
#define GATE_HWV_MM0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp0.c
53
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp0.c
63
#define GATE_MM1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp0.c
64
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp0.c
73
#define GATE_HWV_MM1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp0.c
74
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp1.c
42
#define GATE_MM10(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-disp1.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp1.c
52
#define GATE_HWV_MM10(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp1.c
53
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp1.c
63
#define GATE_MM11(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-disp1.c
64
.id = _id, \
drivers/clk/mediatek/clk-mt8196-disp1.c
73
#define GATE_HWV_MM11(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-disp1.c
74
.id = _id, \
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
24
#define GATE_IMP(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
25
.id = _id, \
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
61
#define GATE_HWV_IMPN(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
62
.id = _id, \
drivers/clk/mediatek/clk-mt8196-mcu.c
45
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
drivers/clk/mediatek/clk-mt8196-mcu.c
50
.id = _id, \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
36
#define GATE_MDP0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
37
.id = _id, \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
46
#define GATE_MDP1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
47
.id = _id, \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
55
#define GATE_MDP2(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-mdpsys.c
56
.id = _id, \
drivers/clk/mediatek/clk-mt8196-mfg.c
37
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
drivers/clk/mediatek/clk-mt8196-mfg.c
42
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ovl0.c
42
#define GATE_HWV_OVL0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ovl0.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ovl0.c
53
#define GATE_HWV_OVL1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ovl0.c
54
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ovl1.c
42
#define GATE_HWV_OVL10(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ovl1.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ovl1.c
53
#define GATE_HWV_OVL11(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ovl1.c
54
.id = _id, \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
42
#define GATE_PERI_AO0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
51
#define GATE_PERI_AO1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
52
.id = _id, \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
60
#define GATE_HWV_PERI_AO1(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-peri_ao.c
61
.id = _id, \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
70
#define GATE_PERI_AO2(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-peri_ao.c
71
.id = _id, \
drivers/clk/mediatek/clk-mt8196-pextp.c
28
#define GATE_PEXT(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-pextp.c
29
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
34
#define GATE_UFSAO0(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
35
.id = _id, \
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
43
#define GATE_UFSAO1(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
44
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
155
#define GATE_HWV_VDE10(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
156
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
166
#define GATE_HWV_VDE11(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
167
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
177
#define GATE_HWV_VDE12(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
178
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
188
#define GATE_HWV_VDE13(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
189
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
199
#define GATE_HWV_VDE14(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
200
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
54
#define GATE_HWV_VDE20(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
55
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
65
#define GATE_HWV_VDE21(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
66
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdec.c
76
#define GATE_HWV_VDE22(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdec.c
77
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
30
#define GATE_MM_AO_V(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
31
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
41
#define GATE_HWV_MM_V(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c
42
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
114
#define GATE_VEN20(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-venc.c
115
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
124
#define GATE_HWV_VEN20(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-venc.c
125
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
135
#define GATE_HWV_VEN21(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-venc.c
136
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
177
#define GATE_HWV_VEN_C20(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-venc.c
178
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
188
#define GATE_HWV_VEN_C21(_id, _name, _parent, _shift) {\
drivers/clk/mediatek/clk-mt8196-venc.c
189
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
42
#define GATE_VEN10(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-venc.c
43
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
52
#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \
drivers/clk/mediatek/clk-mt8196-venc.c
53
.id = _id, \
drivers/clk/mediatek/clk-mt8196-venc.c
64
#define GATE_HWV_VEN10(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8196-venc.c
65
GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
drivers/clk/mediatek/clk-mt8196-venc.c
67
#define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \
drivers/clk/mediatek/clk-mt8196-venc.c
68
.id = _id, \
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
143
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
147
.id = _id, \
drivers/clk/mediatek/clk-mt8365-apmixedsys.c
19
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8365-apmixedsys.c
23
.id = _id, \
drivers/clk/mediatek/clk-mt8365-apmixedsys.c
45
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8365-apmixedsys.c
49
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
drivers/clk/mediatek/clk-mt8365-apu.c
19
#define GATE_APU(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-apu.c
20
GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-cam.c
19
#define GATE_CAM(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-cam.c
20
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-mfg.c
25
#define GATE_MFG0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-mfg.c
26
GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-mfg.c
29
#define GATE_MFG1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-mfg.c
30
GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-mm.c
26
#define GATE_MM0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-mm.c
27
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-mm.c
30
#define GATE_MM1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-mm.c
31
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-vdec.c
25
#define GATE_VDEC0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-vdec.c
26
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-vdec.c
29
#define GATE_VDEC1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-vdec.c
30
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365-venc.c
19
#define GATE_VENC(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365-venc.c
20
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
drivers/clk/mediatek/clk-mt8365.c
542
#define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \
drivers/clk/mediatek/clk-mt8365.c
543
.id = _id, \
drivers/clk/mediatek/clk-mt8365.c
591
#define GATE_TOP0(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
592
GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
drivers/clk/mediatek/clk-mt8365.c
595
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
596
GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
drivers/clk/mediatek/clk-mt8365.c
599
#define GATE_TOP2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
600
GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
drivers/clk/mediatek/clk-mt8365.c
655
#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \
drivers/clk/mediatek/clk-mt8365.c
656
GATE_MTK(_id, _name, _parent, _regs, _shift, \
drivers/clk/mediatek/clk-mt8365.c
659
#define GATE_IFR2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
660
GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs)
drivers/clk/mediatek/clk-mt8365.c
662
#define GATE_IFR3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
663
GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs)
drivers/clk/mediatek/clk-mt8365.c
665
#define GATE_IFR4(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
666
GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs)
drivers/clk/mediatek/clk-mt8365.c
668
#define GATE_IFR5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
669
GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs)
drivers/clk/mediatek/clk-mt8365.c
671
#define GATE_IFR6(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8365.c
672
GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs)
drivers/clk/mediatek/clk-mt8516-apmixedsys.c
23
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8516-apmixedsys.c
26
.id = _id, \
drivers/clk/mediatek/clk-mt8516-apmixedsys.c
43
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8516-apmixedsys.c
46
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
drivers/clk/mediatek/clk-mt8516-aud.c
24
#define GATE_AUD(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516-aud.c
25
GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
drivers/clk/mediatek/clk-mt8516.c
469
#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
drivers/clk/mediatek/clk-mt8516.c
470
.id = _id, \
drivers/clk/mediatek/clk-mt8516.c
529
#define GATE_TOP1(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
530
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8516.c
532
#define GATE_TOP2(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
533
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8516.c
535
#define GATE_TOP2_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
536
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8516.c
538
#define GATE_TOP3(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
539
GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mt8516.c
541
#define GATE_TOP4_I(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
542
GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
drivers/clk/mediatek/clk-mt8516.c
544
#define GATE_TOP5(_id, _name, _parent, _shift) \
drivers/clk/mediatek/clk-mt8516.c
545
GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
drivers/clk/mediatek/clk-mtk.h
114
#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
drivers/clk/mediatek/clk-mtk.h
116
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
134
#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
drivers/clk/mediatek/clk-mtk.h
136
MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
drivers/clk/mediatek/clk-mtk.h
143
#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
drivers/clk/mediatek/clk-mtk.h
144
MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
drivers/clk/mediatek/clk-mtk.h
147
#define MUX(_id, _name, _parents, _reg, _shift, _width) \
drivers/clk/mediatek/clk-mtk.h
148
MUX_FLAGS(_id, _name, _parents, _reg, \
drivers/clk/mediatek/clk-mtk.h
151
#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
drivers/clk/mediatek/clk-mtk.h
152
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
164
#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
drivers/clk/mediatek/clk-mtk.h
166
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
178
#define MUX_DIV_GATE(_id, _name, _parents, \
drivers/clk/mediatek/clk-mtk.h
182
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
217
#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
drivers/clk/mediatek/clk-mtk.h
218
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
39
#define GATE_DUMMY(_id, _name) { \
drivers/clk/mediatek/clk-mtk.h
40
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
53
#define FIXED_CLK(_id, _name, _parent, _rate) { \
drivers/clk/mediatek/clk-mtk.h
54
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
74
#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \
drivers/clk/mediatek/clk-mtk.h
75
.id = _id, \
drivers/clk/mediatek/clk-mtk.h
83
#define FACTOR(_id, _name, _parent, _mult, _div) \
drivers/clk/mediatek/clk-mtk.h
84
FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
drivers/clk/mediatek/clk-mux.h
100
GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
105
#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
108
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
113
#define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
116
MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, \
drivers/clk/mediatek/clk-mux.h
121
#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
124
GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
129
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
134
.id = _id, \
drivers/clk/mediatek/clk-mux.h
155
#define MUX_GATE_HWV_FENC_CLR_SET_UPD(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
160
MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
166
#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
170
.id = _id, \
drivers/clk/mediatek/clk-mux.h
189
#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
193
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
199
#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
203
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
47
#define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
51
.id = _id, \
drivers/clk/mediatek/clk-mux.h
68
#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
71
__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
76
#define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \
drivers/clk/mediatek/clk-mux.h
79
__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
drivers/clk/mediatek/clk-mux.h
89
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
92
GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
drivers/clk/mediatek/clk-mux.h
97
#define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \
drivers/clk/microchip/clk-mpfs-ccc.c
101
#define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \
drivers/clk/microchip/clk-mpfs-ccc.c
102
.id = _id, \
drivers/clk/microchip/clk-mpfs-ccc.c
124
#define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \
drivers/clk/microchip/clk-mpfs-ccc.c
125
.id = _id, \
drivers/clk/microchip/clk-mpfs.c
166
#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
drivers/clk/microchip/clk-mpfs.c
167
.id = _id, \
drivers/clk/microchip/clk-mpfs.c
205
#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \
drivers/clk/microchip/clk-mpfs.c
206
.id = _id, \
drivers/clk/microchip/clk-mpfs.c
299
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
drivers/clk/microchip/clk-mpfs.c
300
.id = _id, \
drivers/clk/microchip/clk-mpfs.c
395
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
drivers/clk/microchip/clk-mpfs.c
396
.id = _id, \
drivers/clk/nxp/clk-lpc18xx-cgu.c
169
#define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \
drivers/clk/nxp/clk-lpc18xx-cgu.c
171
.clk_id = CLK_SRC_ ##_id, \
drivers/clk/nxp/clk-lpc18xx-cgu.c
203
#define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \
drivers/clk/nxp/clk-lpc18xx-cgu.c
205
.clk_id = BASE_ ##_id ##_CLK, \
drivers/clk/nxp/clk-lpc18xx-cgu.c
268
#define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \
drivers/clk/nxp/clk-lpc18xx-cgu.c
270
.clk_id = CLK_SRC_ ##_id, \
drivers/clk/nxp/clk-lpc18xx-cgu.c
272
.reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \
drivers/clk/pistachio/clk.h
119
#define PLL(_id, _name, _pname, _type, _reg, _rates) \
drivers/clk/pistachio/clk.h
121
.id = _id, \
drivers/clk/pistachio/clk.h
130
#define PLL_FIXED(_id, _name, _pname, _type, _reg) \
drivers/clk/pistachio/clk.h
132
.id = _id, \
drivers/clk/pistachio/clk.h
19
#define GATE(_id, _name, _pname, _reg, _shift) \
drivers/clk/pistachio/clk.h
21
.id = _id, \
drivers/clk/pistachio/clk.h
39
#define MUX(_id, _name, _pnames, _reg, _shift) \
drivers/clk/pistachio/clk.h
41
.id = _id, \
drivers/clk/pistachio/clk.h
59
#define DIV(_id, _name, _pname, _reg, _width) \
drivers/clk/pistachio/clk.h
61
.id = _id, \
drivers/clk/pistachio/clk.h
69
#define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \
drivers/clk/pistachio/clk.h
71
.id = _id, \
drivers/clk/pistachio/clk.h
86
#define FIXED_FACTOR(_id, _name, _pname, _div) \
drivers/clk/pistachio/clk.h
88
.id = _id, \
drivers/clk/qcom/ipq-cmn-pll.c
98
#define CLK_PLL_OUTPUT(_id, _name, _rate) { \
drivers/clk/qcom/ipq-cmn-pll.c
99
.id = _id, \
drivers/clk/ralink/clk-mt7621.c
184
#define FIXED(_id, _name, _rate) \
drivers/clk/ralink/clk-mt7621.c
186
.idx = _id, \
drivers/clk/ralink/clk-mt7621.c
62
#define GATE(_id, _name, _pname, _shift) \
drivers/clk/ralink/clk-mt7621.c
64
.idx = _id, \
drivers/clk/renesas/r8a779a0-cpg-mssr.c
61
#define DEF_PLL(_name, _id, _offset) \
drivers/clk/renesas/r8a779a0-cpg-mssr.c
62
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
drivers/clk/renesas/r9a08g045-cpg.c
56
#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
drivers/clk/renesas/r9a08g045-cpg.c
57
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
drivers/clk/renesas/r9a09g077-cpg.c
76
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
drivers/clk/renesas/r9a09g077-cpg.c
77
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
drivers/clk/renesas/r9a09g077-cpg.c
79
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
drivers/clk/renesas/r9a09g077-cpg.c
80
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
drivers/clk/renesas/r9a09g077-cpg.c
83
#define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \
drivers/clk/renesas/r9a09g077-cpg.c
84
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
drivers/clk/renesas/rcar-gen3-cpg.h
37
#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
drivers/clk/renesas/rcar-gen3-cpg.h
38
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
drivers/clk/renesas/rcar-gen3-cpg.h
40
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
drivers/clk/renesas/rcar-gen3-cpg.h
41
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
drivers/clk/renesas/rcar-gen3-cpg.h
43
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
drivers/clk/renesas/rcar-gen3-cpg.h
44
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
drivers/clk/renesas/rcar-gen3-cpg.h
48
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
drivers/clk/renesas/rcar-gen3-cpg.h
50
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
drivers/clk/renesas/rcar-gen3-cpg.h
53
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
drivers/clk/renesas/rcar-gen3-cpg.h
54
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
drivers/clk/renesas/rcar-gen3-cpg.h
56
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
drivers/clk/renesas/rcar-gen3-cpg.h
57
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
drivers/clk/renesas/rcar-gen3-cpg.h
60
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
drivers/clk/renesas/rcar-gen3-cpg.h
61
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
drivers/clk/renesas/rcar-gen3-cpg.h
63
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
drivers/clk/renesas/rcar-gen3-cpg.h
64
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
drivers/clk/renesas/rcar-gen3-cpg.h
66
#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
drivers/clk/renesas/rcar-gen3-cpg.h
67
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
drivers/clk/renesas/rcar-gen4-cpg.h
35
#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
drivers/clk/renesas/rcar-gen4-cpg.h
36
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
drivers/clk/renesas/rcar-gen4-cpg.h
38
#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
drivers/clk/renesas/rcar-gen4-cpg.h
39
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
drivers/clk/renesas/rcar-gen4-cpg.h
41
#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
drivers/clk/renesas/rcar-gen4-cpg.h
42
DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
drivers/clk/renesas/rcar-gen4-cpg.h
46
#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
drivers/clk/renesas/rcar-gen4-cpg.h
47
DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
drivers/clk/renesas/rcar-gen4-cpg.h
49
#define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \
drivers/clk/renesas/rcar-gen4-cpg.h
50
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx)
drivers/clk/renesas/rcar-gen4-cpg.h
52
#define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \
drivers/clk/renesas/rcar-gen4-cpg.h
53
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx)
drivers/clk/renesas/rcar-gen4-cpg.h
55
#define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \
drivers/clk/renesas/rcar-gen4-cpg.h
56
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F9_24, _parent, .offset = _idx)
drivers/clk/renesas/rcar-gen4-cpg.h
58
#define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \
drivers/clk/renesas/rcar-gen4-cpg.h
59
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx)
drivers/clk/renesas/rcar-gen4-cpg.h
61
#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
drivers/clk/renesas/rcar-gen4-cpg.h
62
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
drivers/clk/renesas/renesas-cpg-mssr.h
71
#define DEF_TYPE(_name, _id, _type...) \
drivers/clk/renesas/renesas-cpg-mssr.h
72
{ .name = _name, .id = _id, .type = _type }
drivers/clk/renesas/renesas-cpg-mssr.h
73
#define DEF_BASE(_name, _id, _type, _parent...) \
drivers/clk/renesas/renesas-cpg-mssr.h
74
DEF_TYPE(_name, _id, _type, .parent = _parent)
drivers/clk/renesas/renesas-cpg-mssr.h
76
#define DEF_INPUT(_name, _id) \
drivers/clk/renesas/renesas-cpg-mssr.h
77
DEF_TYPE(_name, _id, CLK_TYPE_IN)
drivers/clk/renesas/renesas-cpg-mssr.h
78
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
drivers/clk/renesas/renesas-cpg-mssr.h
79
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
drivers/clk/renesas/renesas-cpg-mssr.h
80
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
drivers/clk/renesas/renesas-cpg-mssr.h
81
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
drivers/clk/renesas/renesas-cpg-mssr.h
82
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
drivers/clk/renesas/renesas-cpg-mssr.h
83
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
drivers/clk/renesas/renesas-cpg-mssr.h
84
#define DEF_RATE(_name, _id, _rate) \
drivers/clk/renesas/renesas-cpg-mssr.h
85
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
drivers/clk/renesas/rzg2l-cpg.h
149
#define DEF_TYPE(_name, _id, _type...) \
drivers/clk/renesas/rzg2l-cpg.h
150
{ .name = _name, .id = _id, .type = _type }
drivers/clk/renesas/rzg2l-cpg.h
151
#define DEF_BASE(_name, _id, _type, _parent...) \
drivers/clk/renesas/rzg2l-cpg.h
152
DEF_TYPE(_name, _id, _type, .parent = _parent)
drivers/clk/renesas/rzg2l-cpg.h
153
#define DEF_SAMPLL(_name, _id, _parent, _conf) \
drivers/clk/renesas/rzg2l-cpg.h
154
DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
drivers/clk/renesas/rzg2l-cpg.h
155
#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
drivers/clk/renesas/rzg2l-cpg.h
156
DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
158
#define DEF_INPUT(_name, _id) \
drivers/clk/renesas/rzg2l-cpg.h
159
DEF_TYPE(_name, _id, CLK_TYPE_IN)
drivers/clk/renesas/rzg2l-cpg.h
160
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
drivers/clk/renesas/rzg2l-cpg.h
161
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
drivers/clk/renesas/rzg2l-cpg.h
162
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
drivers/clk/renesas/rzg2l-cpg.h
163
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
166
#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
drivers/clk/renesas/rzg2l-cpg.h
167
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
170
#define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \
drivers/clk/renesas/rzg2l-cpg.h
172
DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \
drivers/clk/renesas/rzg2l-cpg.h
177
#define DEF_MUX(_name, _id, _conf, _parent_names) \
drivers/clk/renesas/rzg2l-cpg.h
178
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
182
#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
drivers/clk/renesas/rzg2l-cpg.h
183
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
187
#define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \
drivers/clk/renesas/rzg2l-cpg.h
188
DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \
drivers/clk/renesas/rzg2l-cpg.h
192
#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
drivers/clk/renesas/rzg2l-cpg.h
193
DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
drivers/clk/renesas/rzg2l-cpg.h
194
#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
drivers/clk/renesas/rzg2l-cpg.h
195
DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
drivers/clk/renesas/rzg2l-cpg.h
198
#define DEF_DSI_DIV(_name, _id, _parent, _flag) \
drivers/clk/renesas/rzg2l-cpg.h
199
DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
drivers/clk/renesas/rzg2l-cpg.h
222
#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \
drivers/clk/renesas/rzg2l-cpg.h
225
.id = MOD_CLK_BASE + (_id), \
drivers/clk/renesas/rzg2l-cpg.h
233
#define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \
drivers/clk/renesas/rzg2l-cpg.h
234
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
drivers/clk/renesas/rzg2l-cpg.h
236
#define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \
drivers/clk/renesas/rzg2l-cpg.h
237
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
drivers/clk/renesas/rzg2l-cpg.h
252
#define DEF_RST_MON(_id, _off, _bit, _monbit) \
drivers/clk/renesas/rzg2l-cpg.h
253
[_id] = { \
drivers/clk/renesas/rzg2l-cpg.h
258
#define DEF_RST(_id, _off, _bit) \
drivers/clk/renesas/rzg2l-cpg.h
259
DEF_RST_MON(_id, _off, _bit, -1)
drivers/clk/renesas/rzv2h-cpg.h
208
#define DEF_TYPE(_name, _id, _type...) \
drivers/clk/renesas/rzv2h-cpg.h
209
{ .name = _name, .id = _id, .type = _type }
drivers/clk/renesas/rzv2h-cpg.h
210
#define DEF_BASE(_name, _id, _type, _parent...) \
drivers/clk/renesas/rzv2h-cpg.h
211
DEF_TYPE(_name, _id, _type, .parent = _parent)
drivers/clk/renesas/rzv2h-cpg.h
212
#define DEF_PLL(_name, _id, _parent, _pll_packed) \
drivers/clk/renesas/rzv2h-cpg.h
213
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
drivers/clk/renesas/rzv2h-cpg.h
214
#define DEF_INPUT(_name, _id) \
drivers/clk/renesas/rzv2h-cpg.h
215
DEF_TYPE(_name, _id, CLK_TYPE_IN)
drivers/clk/renesas/rzv2h-cpg.h
216
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
drivers/clk/renesas/rzv2h-cpg.h
217
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
drivers/clk/renesas/rzv2h-cpg.h
218
#define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \
drivers/clk/renesas/rzv2h-cpg.h
219
DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \
drivers/clk/renesas/rzv2h-cpg.h
221
#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
drivers/clk/renesas/rzv2h-cpg.h
222
DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
drivers/clk/renesas/rzv2h-cpg.h
227
#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
drivers/clk/renesas/rzv2h-cpg.h
228
DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
drivers/clk/renesas/rzv2h-cpg.h
229
#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
drivers/clk/renesas/rzv2h-cpg.h
230
DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
drivers/clk/renesas/rzv2h-cpg.h
236
#define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \
drivers/clk/renesas/rzv2h-cpg.h
237
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed)
drivers/clk/renesas/rzv2h-cpg.h
238
#define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \
drivers/clk/renesas/rzv2h-cpg.h
239
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \
drivers/clk/rockchip/clk.h
1002
#define MUX(_id, cname, pnames, f, o, s, w, mf) \
drivers/clk/rockchip/clk.h
1004
.id = _id, \
drivers/clk/rockchip/clk.h
1017
#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
drivers/clk/rockchip/clk.h
1019
.id = _id, \
drivers/clk/rockchip/clk.h
1033
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
drivers/clk/rockchip/clk.h
1035
.id = _id, \
drivers/clk/rockchip/clk.h
1049
#define DIV(_id, cname, pname, f, o, s, w, df) \
drivers/clk/rockchip/clk.h
1051
.id = _id, \
drivers/clk/rockchip/clk.h
1064
#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
drivers/clk/rockchip/clk.h
1066
.id = _id, \
drivers/clk/rockchip/clk.h
1079
#define GATE(_id, cname, pname, f, o, b, gf) \
drivers/clk/rockchip/clk.h
1081
.id = _id, \
drivers/clk/rockchip/clk.h
1092
#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
drivers/clk/rockchip/clk.h
1094
.id = _id, \
drivers/clk/rockchip/clk.h
1106
#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
drivers/clk/rockchip/clk.h
1108
.id = _id, \
drivers/clk/rockchip/clk.h
1120
#define MMC(_id, cname, pname, offset, shift) \
drivers/clk/rockchip/clk.h
1122
.id = _id, \
drivers/clk/rockchip/clk.h
1131
#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
drivers/clk/rockchip/clk.h
1133
.id = _id, \
drivers/clk/rockchip/clk.h
1143
#define INVERTER(_id, cname, pname, io, is, if) \
drivers/clk/rockchip/clk.h
1145
.id = _id, \
drivers/clk/rockchip/clk.h
1155
#define FACTOR(_id, cname, pname, f, fm, fd) \
drivers/clk/rockchip/clk.h
1157
.id = _id, \
drivers/clk/rockchip/clk.h
1167
#define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
drivers/clk/rockchip/clk.h
1169
.id = _id, \
drivers/clk/rockchip/clk.h
1182
#define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
drivers/clk/rockchip/clk.h
1185
.id = _id, \
drivers/clk/rockchip/clk.h
1203
#define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
drivers/clk/rockchip/clk.h
1206
.id = _id, \
drivers/clk/rockchip/clk.h
1222
#define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
drivers/clk/rockchip/clk.h
1225
.id = _id, \
drivers/clk/rockchip/clk.h
1240
#define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
drivers/clk/rockchip/clk.h
1242
.id = _id, \
drivers/clk/rockchip/clk.h
1256
#define SGRF_GATE(_id, cname, pname) \
drivers/clk/rockchip/clk.h
1257
FACTOR(_id, cname, pname, 0, 1, 1)
drivers/clk/rockchip/clk.h
635
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
drivers/clk/rockchip/clk.h
638
.id = _id, \
drivers/clk/rockchip/clk.h
796
#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
drivers/clk/rockchip/clk.h
799
.id = _id, \
drivers/clk/rockchip/clk.h
817
#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
drivers/clk/rockchip/clk.h
820
.id = _id, \
drivers/clk/rockchip/clk.h
839
#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
drivers/clk/rockchip/clk.h
842
.id = _id, \
drivers/clk/rockchip/clk.h
857
#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
drivers/clk/rockchip/clk.h
860
.id = _id, \
drivers/clk/rockchip/clk.h
876
#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
drivers/clk/rockchip/clk.h
879
.id = _id, \
drivers/clk/rockchip/clk.h
894
#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
drivers/clk/rockchip/clk.h
897
.id = _id, \
drivers/clk/rockchip/clk.h
913
#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
drivers/clk/rockchip/clk.h
916
.id = _id, \
drivers/clk/rockchip/clk.h
933
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
drivers/clk/rockchip/clk.h
935
.id = _id, \
drivers/clk/rockchip/clk.h
950
#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
drivers/clk/rockchip/clk.h
952
.id = _id, \
drivers/clk/rockchip/clk.h
968
#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
drivers/clk/rockchip/clk.h
970
.id = _id, \
drivers/clk/rockchip/clk.h
984
#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
drivers/clk/rockchip/clk.h
987
.id = _id, \
drivers/clk/samsung/clk-s3c64xx.c
48
#define GATE_BUS(_id, cname, pname, o, b) \
drivers/clk/samsung/clk-s3c64xx.c
49
GATE(_id, cname, pname, o, b, 0, 0)
drivers/clk/samsung/clk-s3c64xx.c
50
#define GATE_SCLK(_id, cname, pname, o, b) \
drivers/clk/samsung/clk-s3c64xx.c
51
GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
drivers/clk/samsung/clk-s3c64xx.c
52
#define GATE_ON(_id, cname, pname, o, b) \
drivers/clk/samsung/clk-s3c64xx.c
53
GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
drivers/clk/samsung/clk.h
110
#define FFACTOR(_id, cname, pname, m, d, f) \
drivers/clk/samsung/clk.h
112
.id = _id, \
drivers/clk/samsung/clk.h
144
#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
drivers/clk/samsung/clk.h
146
.id = _id, \
drivers/clk/samsung/clk.h
157
#define MUX(_id, cname, pnames, o, s, w) \
drivers/clk/samsung/clk.h
158
__MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
drivers/clk/samsung/clk.h
160
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
drivers/clk/samsung/clk.h
161
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)
drivers/clk/samsung/clk.h
164
#define nMUX(_id, cname, pnames, o, s, w) \
drivers/clk/samsung/clk.h
165
__MUX(_id, cname, pnames, o, s, w, 0, 0)
drivers/clk/samsung/clk.h
167
#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
drivers/clk/samsung/clk.h
168
__MUX(_id, cname, pnames, o, s, w, f, mf)
drivers/clk/samsung/clk.h
194
#define __DIV(_id, cname, pname, o, s, w, f, df, t) \
drivers/clk/samsung/clk.h
196
.id = _id, \
drivers/clk/samsung/clk.h
207
#define DIV(_id, cname, pname, o, s, w) \
drivers/clk/samsung/clk.h
208
__DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
drivers/clk/samsung/clk.h
210
#define DIV_F(_id, cname, pname, o, s, w, f, df) \
drivers/clk/samsung/clk.h
211
__DIV(_id, cname, pname, o, s, w, f, df, NULL)
drivers/clk/samsung/clk.h
213
#define DIV_T(_id, cname, pname, o, s, w, t) \
drivers/clk/samsung/clk.h
214
__DIV(_id, cname, pname, o, s, w, 0, 0, t)
drivers/clk/samsung/clk.h
236
#define __GATE(_id, cname, pname, o, b, f, gf) \
drivers/clk/samsung/clk.h
238
.id = _id, \
drivers/clk/samsung/clk.h
247
#define GATE(_id, cname, pname, o, b, f, gf) \
drivers/clk/samsung/clk.h
248
__GATE(_id, cname, pname, o, b, f, gf)
drivers/clk/samsung/clk.h
284
#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
drivers/clk/samsung/clk.h
286
.id = _id, \
drivers/clk/samsung/clk.h
296
#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
drivers/clk/samsung/clk.h
297
__PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
drivers/clk/samsung/clk.h
311
#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _layout, _cfg) \
drivers/clk/samsung/clk.h
313
.id = _id, \
drivers/clk/samsung/clk.h
58
#define ALIAS(_id, dname, a) \
drivers/clk/samsung/clk.h
60
.id = _id, \
drivers/clk/samsung/clk.h
83
#define FRATE(_id, cname, pname, f, frate) \
drivers/clk/samsung/clk.h
85
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
273
#define SG2042_DIV_FW(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
276
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
289
#define SG2042_DIV_FW_RO(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
292
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
305
#define SG2042_DIV_HW(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
308
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
321
#define SG2042_DIV_HW_RO(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
324
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
337
#define SG2042_DIV_HWS(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
340
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
353
#define SG2042_DIV_HWS_RO(_id, _name, _parent, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
356
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
369
#define SG2042_GATE_HWS(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
371
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
381
#define SG2042_GATE_HW(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
383
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
393
#define SG2042_GATE_FW(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
395
.id = _id, \
drivers/clk/sophgo/clk-sg2042-clkgen.c
405
#define SG2042_MUX(_id, _name, _parents, _flags, _r_select, _shift, _width) { \
drivers/clk/sophgo/clk-sg2042-clkgen.c
406
.id = _id, \
drivers/clk/sophgo/clk-sg2042-pll.c
427
#define SG2042_PLL_FW(_id, _name, _parent, _r_ctrl, _shift) \
drivers/clk/sophgo/clk-sg2042-pll.c
429
.id = _id, \
drivers/clk/sophgo/clk-sg2042-pll.c
441
#define SG2042_PLL_FW_RO(_id, _name, _parent, _r_ctrl, _shift) \
drivers/clk/sophgo/clk-sg2042-pll.c
443
.id = _id, \
drivers/clk/sophgo/clk-sg2042-rpgate.c
72
#define SG2042_GATE_FW(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2042-rpgate.c
79
.id = _id, \
drivers/clk/sophgo/clk-sg2044-pll.c
385
#define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \
drivers/clk/sophgo/clk-sg2044-pll.c
389
.id = (_id), \
drivers/clk/sophgo/clk-sg2044-pll.c
392
#define DEFINE_SG2044_PLL(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044-pll.c
399
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044-pll.c
413
#define DEFINE_SG2044_PLL_RO(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044-pll.c
420
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
288
#define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \
drivers/clk/sophgo/clk-sg2044.c
292
.id = (_id), \
drivers/clk/sophgo/clk-sg2044.c
295
#define SG2044_CLK_COMMON_PHWS(_id, _name, _parents, _op, _flags) \
drivers/clk/sophgo/clk-sg2044.c
299
.id = (_id), \
drivers/clk/sophgo/clk-sg2044.c
302
#define DEFINE_SG2044_GATEABLE_DIV(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
306
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
318
#define DEFINE_SG2044_DIV(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
322
.common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
334
#define DEFINE_SG2044_DIV_PDATA(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
338
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
350
#define DEFINE_SG2044_DIV_RO(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
354
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
366
#define DEFINE_SG2044_MUX(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
370
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
drivers/clk/sophgo/clk-sg2044.c
380
#define DEFINE_SG2044_GATE(_id, _name, _parent, _flags, \
drivers/clk/sophgo/clk-sg2044.c
383
.common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \
drivers/clk/stm32/clk-stm32mp1.c
1173
#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1175
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1187
#define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
drivers/clk/stm32/clk-stm32mp1.c
1189
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1200
#define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
drivers/clk/stm32/clk-stm32mp1.c
1203
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1217
#define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1218
DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
drivers/clk/stm32/clk-stm32mp1.c
1221
#define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1223
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1237
#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
drivers/clk/stm32/clk-stm32mp1.c
1239
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1264
#define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
drivers/clk/stm32/clk-stm32mp1.c
1265
GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
drivers/clk/stm32/clk-stm32mp1.c
1269
#define STM32_GATE(_id, _name, _parent, _flags, _gate)\
drivers/clk/stm32/clk-stm32mp1.c
1271
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1279
#define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\
drivers/clk/stm32/clk-stm32mp1.c
1281
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1314
#define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1315
STM32_GATE(_id, _name, _parent, _flags,\
drivers/clk/stm32/clk-stm32mp1.c
1318
#define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
drivers/clk/stm32/clk-stm32mp1.c
1319
STM32_GATE(_id, _name, _parent, _flags,\
drivers/clk/stm32/clk-stm32mp1.c
1322
#define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\
drivers/clk/stm32/clk-stm32mp1.c
1323
STM32_GATE_PDATA(_id, _name, _parent, _flags,\
drivers/clk/stm32/clk-stm32mp1.c
1371
#define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
drivers/clk/stm32/clk-stm32mp1.c
1373
.id = _id,\
drivers/clk/stm32/clk-stm32mp1.c
1386
#define PCLK(_id, _name, _parent, _flags, _mgate)\
drivers/clk/stm32/clk-stm32mp1.c
1387
MGATE_MP1(_id, _name, _parent, _flags, _mgate)
drivers/clk/stm32/clk-stm32mp1.c
1389
#define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\
drivers/clk/stm32/clk-stm32mp1.c
1390
MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)
drivers/clk/stm32/clk-stm32mp1.c
1392
#define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
drivers/clk/stm32/clk-stm32mp1.c
1393
COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
drivers/clk/stm32/clk-stm32mp1.c
1516
#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
drivers/clk/stm32/clk-stm32mp1.c
1518
[_id] = {\
drivers/clk/stm32/clk-stm32mp1.c
1528
#define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1529
_K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
drivers/clk/stm32/clk-stm32mp1.c
1532
#define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1533
_K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
drivers/clk/stm32/clk-stm32mp1.c
1534
&mp1_mgate[_id], &mp1_mgate_clk_ops)
drivers/clk/stm32/clk-stm32mp1.c
1701
#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
drivers/clk/stm32/clk-stm32mp1.c
1702
[_id] = {\
drivers/clk/stm32/clk-stm32mp1.c
1714
#define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1715
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
drivers/clk/stm32/clk-stm32mp1.c
1718
#define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
drivers/clk/stm32/clk-stm32mp1.c
1719
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
drivers/clk/stm32/clk-stm32mp1.c
1720
&ker_mux[_id], &clk_mmux_ops)
drivers/clk/stm32/clk-stm32mp13.c
140
#define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\
drivers/clk/stm32/clk-stm32mp13.c
141
[(_id)] = {\
drivers/clk/stm32/clk-stm32mp13.c
147
#define CFG_GATE(_id, _offset, _bit_idx)\
drivers/clk/stm32/clk-stm32mp13.c
148
_CFG_GATE(_id, _offset, _bit_idx, 0)
drivers/clk/stm32/clk-stm32mp13.c
150
#define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\
drivers/clk/stm32/clk-stm32mp13.c
151
_CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
drivers/clk/stm32/clk-stm32mp13.c
290
#define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\
drivers/clk/stm32/clk-stm32mp13.c
291
[(_id)] = {\
drivers/clk/stm32/clk-stm32mp13.c
352
#define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\
drivers/clk/stm32/clk-stm32mp13.c
353
[_id] = {\
drivers/clk/stm32/clk-stm32mp13.c
361
#define CFG_MUX(_id, _offset, _shift, _witdh)\
drivers/clk/stm32/clk-stm32mp13.c
362
_CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
drivers/clk/stm32/clk-stm32mp13.c
364
#define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\
drivers/clk/stm32/clk-stm32mp13.c
365
_CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, MUX_SAFE)
drivers/clk/stm32/clk-stm32mp21.c
44
#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG)
drivers/clk/stm32/clk-stm32mp25.c
42
#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG)
drivers/clk/tegra/clk-tegra-periph.c
266
#define MUX_I2S_SPDIF(_id) \
drivers/clk/tegra/clk-tegra-periph.c
267
static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
drivers/clk/tegra/clk-tegra-periph.c
268
#_id, "pll_p",\
drivers/clk/tegra/clk-tegra-periph.c
838
#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
drivers/clk/tegra/clk-tegra-periph.c
847
.clk_id = tegra_clk_ ## _id,\
drivers/clk/x86/clk-cgu.h
117
#define LGM_PLL(_id, _name, _pdata, _flags, \
drivers/clk/x86/clk-cgu.h
120
.id = _id, \
drivers/clk/x86/clk-cgu.h
146
#define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
drivers/clk/x86/clk-cgu.h
150
.id = _id, \
drivers/clk/x86/clk-cgu.h
203
#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
drivers/clk/x86/clk-cgu.h
206
.id = _id, \
drivers/clk/x86/clk-cgu.h
219
#define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
drivers/clk/x86/clk-cgu.h
222
.id = _id, \
drivers/clk/x86/clk-cgu.h
241
#define LGM_GATE(_id, _name, _pname, _f, _reg, \
drivers/clk/x86/clk-cgu.h
244
.id = _id, \
drivers/clk/x86/clk-cgu.h
259
#define LGM_FIXED(_id, _name, _pname, _f, _reg, \
drivers/clk/x86/clk-cgu.h
262
.id = _id, \
drivers/clk/x86/clk-cgu.h
279
#define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
drivers/clk/x86/clk-cgu.h
282
.id = _id, \
drivers/counter/104-quad-8.c
1077
#define QUAD8_QUAD_SIGNAL(_id, _name) { \
drivers/counter/104-quad-8.c
1078
.id = (_id), \
drivers/counter/104-quad-8.c
1084
#define QUAD8_INDEX_SIGNAL(_id, _name) { \
drivers/counter/104-quad-8.c
1085
.id = (_id), \
drivers/counter/104-quad-8.c
1118
#define QUAD8_COUNT_SYNAPSES(_id) { \
drivers/counter/104-quad-8.c
1122
.signal = quad8_signals + 2 * (_id) \
drivers/counter/104-quad-8.c
1127
.signal = quad8_signals + 2 * (_id) + 1 \
drivers/counter/104-quad-8.c
1132
.signal = quad8_signals + 2 * (_id) + 16 \
drivers/counter/104-quad-8.c
1169
#define QUAD8_COUNT(_id, _cntname) { \
drivers/counter/104-quad-8.c
1170
.id = (_id), \
drivers/counter/104-quad-8.c
1174
.synapses = quad8_count_synapses[(_id)], \
drivers/counter/i8254.c
320
#define I8254_SIGNAL(_id, _name) { \
drivers/counter/i8254.c
321
.id = (_id), \
drivers/counter/i8254.c
339
#define I8254_SYNAPSES_BASE(_id) ((_id) * I8254_SYNAPSES_PER_COUNT)
drivers/counter/i8254.c
340
#define I8254_SYNAPSE_CLK(_id) { \
drivers/counter/i8254.c
343
.signal = &i8254_signals[I8254_SYNAPSES_BASE(_id) + 0], \
drivers/counter/i8254.c
345
#define I8254_SYNAPSE_GATE(_id) { \
drivers/counter/i8254.c
348
.signal = &i8254_signals[I8254_SYNAPSES_BASE(_id) + 1], \
drivers/counter/i8254.c
380
#define I8254_COUNT(_id, _name) { \
drivers/counter/i8254.c
381
.id = (_id), \
drivers/counter/i8254.c
385
.synapses = &i8254_synapses[I8254_SYNAPSES_BASE(_id)], \
drivers/counter/intel-qep.c
152
#define INTEL_QEP_SIGNAL(_id, _name) { \
drivers/counter/intel-qep.c
153
.id = (_id), \
drivers/counter/rz-mtu3-cnt.c
708
#define RZ_MTU3_PHASE_SIGNAL(_id, _name) { \
drivers/counter/rz-mtu3-cnt.c
709
.id = (_id), \
drivers/cxl/core/mbox.c
31
#define CXL_CMD(_id, sin, sout, _flags) \
drivers/cxl/core/mbox.c
32
[CXL_MEM_COMMAND_ID_##_id] = { \
drivers/cxl/core/mbox.c
34
.id = CXL_MEM_COMMAND_ID_##_id, \
drivers/cxl/core/mbox.c
38
.opcode = CXL_MBOX_OP_##_id, \
drivers/dax/bus.c
1573
struct dax_id *dax_id, *_id;
drivers/dax/bus.c
1576
list_for_each_entry_safe(dax_id, _id, &dax_drv->ids, list) {
drivers/dio/dio.c
108
#define dio_getname(_id) (dio_no_name)
drivers/dma/at_hdmac.c
184
({ typeof(id) _id = (id); \
drivers/dma/at_hdmac.c
185
FIELD_PREP(ATC_SRC_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \
drivers/dma/at_hdmac.c
186
FIELD_PREP(ATC_SRC_PER, _id); })
drivers/dma/at_hdmac.c
188
({ typeof(id) _id = (id); \
drivers/dma/at_hdmac.c
189
FIELD_PREP(ATC_DST_PER_MSB, FIELD_GET(ATC_PER_MSB, _id)) | \
drivers/dma/at_hdmac.c
190
FIELD_PREP(ATC_DST_PER, _id); })
drivers/gpio/gpio-104-idi-48.c
89
#define IDI48_REGMAP_IRQ(_id) \
drivers/gpio/gpio-104-idi-48.c
90
[_id] = { \
drivers/gpio/gpio-104-idi-48.c
91
.mask = BIT((_id) / 8), \
drivers/gpio/gpio-104-idio-16.c
72
#define IDIO_16_REGMAP_IRQ(_id) \
drivers/gpio/gpio-104-idio-16.c
73
[16 + _id] = { \
drivers/gpio/gpio-104-idio-16.c
74
.mask = BIT(_id), \
drivers/gpio/gpio-pci-idio-16.c
54
#define IDIO_16_REGMAP_IRQ(_id) \
drivers/gpio/gpio-pci-idio-16.c
55
[16 + _id] = { \
drivers/gpio/gpio-pcie-idio-24.c
123
#define IDIO_24_REGMAP_IRQ(_id) \
drivers/gpio/gpio-pcie-idio-24.c
124
[24 + _id] = { \
drivers/gpio/gpio-pcie-idio-24.c
125
.reg_offset = (_id) / IDIO_24_NGPIO_PER_REG, \
drivers/gpio/gpio-pcie-idio-24.c
126
.mask = BIT((_id) % IDIO_24_NGPIO_PER_REG), \
drivers/gpio/gpio-pcie-idio-24.c
129
#define IDIO_24_IIN_IRQ(_id) IDIO_24_REGMAP_IRQ(_id)
drivers/gpio/gpio-pcie-idio-24.c
130
#define IDIO_24_TTL_IRQ(_id) IDIO_24_REGMAP_IRQ(24 + _id)
drivers/gpio/gpio-ws16c48.c
79
#define WS16C48_REGMAP_IRQ(_id) \
drivers/gpio/gpio-ws16c48.c
80
[_id] = { \
drivers/gpio/gpio-ws16c48.c
81
.reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
drivers/gpio/gpio-ws16c48.c
82
.mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
drivers/gpio/gpio-ws16c48.c
84
.type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
drivers/gpu/drm/amd/pm/amdgpu_pm.c
2505
#define AMDGPU_PM_POLICY_ATTR(_name, _id) \
drivers/gpu/drm/amd/pm/amdgpu_pm.c
2509
.id = PP_PM_POLICY_##_id, \
drivers/gpu/drm/i915/display/intel_display_device.c
1445
#define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) }
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
133
#define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
134
{ .name = #_id, .statetype = _type, .base = _base, \
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
465
#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
59
#define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
60
{ .id = _id, .name = #_id,\
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
613
#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count },
drivers/gpu/drm/panfrost/panfrost_gpu.c
190
#define GPU_MODEL(_name, _id, ...) \
drivers/gpu/drm/panfrost/panfrost_gpu.c
193
.id = _id, \
drivers/gpu/drm/xe/tests/xe_test.h
60
#define xe_cur_kunit_priv(_id) NULL
drivers/hid/hid-uclogic-rdesc.c
661
#define UCLOGIC_RDESC_FRAME_BUTTONS_BYTES(_id, _size) \
drivers/hid/hid-uclogic-rdesc.c
665
0x85, (_id), /* Report ID (_id), */ \
drivers/hwmon/max1111.c
123
#define MAX1111_ADC_ATTR(_id) \
drivers/hwmon/max1111.c
124
SENSOR_DEVICE_ATTR(in##_id##_input, S_IRUGO, show_adc, NULL, _id)
drivers/hwmon/pmbus/pmbus.h
495
#define PMBUS_REGULATOR_STEP(_name, _id, _voltages, _step, _min_uV) \
drivers/hwmon/pmbus/pmbus.h
496
[_id] = { \
drivers/hwmon/pmbus/pmbus.h
497
.name = (_name # _id), \
drivers/hwmon/pmbus/pmbus.h
498
.id = (_id), \
drivers/hwmon/pmbus/pmbus.h
499
.of_match = of_match_ptr(_name # _id), \
drivers/hwmon/pmbus/pmbus.h
510
#define PMBUS_REGULATOR(_name, _id) PMBUS_REGULATOR_STEP(_name, _id, 0, 0, 0)
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
181
#define EXT_CAP(_id, _highest_mandatory_reg_offset, _parser) \
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
182
{ .id = (_id), .parser = (_parser), \
drivers/iio/adc/bcm_iproc_adc.c
486
#define IPROC_ADC_CHANNEL(_index, _id) { \
drivers/iio/adc/bcm_iproc_adc.c
492
.datasheet_name = _id, \
drivers/iio/adc/da9150-gpadc.c
250
#define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \
drivers/iio/adc/da9150-gpadc.c
254
.channel = DA9150_GPADC_CHAN_##_id, \
drivers/iio/adc/da9150-gpadc.c
258
.datasheet_name = #_id, \
drivers/iio/adc/da9150-gpadc.c
261
#define DA9150_GPADC_CHANNEL_RAW(_id, _hw_id, _type, _ext_name) \
drivers/iio/adc/da9150-gpadc.c
262
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
drivers/iio/adc/da9150-gpadc.c
265
#define DA9150_GPADC_CHANNEL_SCALED(_id, _hw_id, _type, _ext_name) \
drivers/iio/adc/da9150-gpadc.c
266
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
drivers/iio/adc/da9150-gpadc.c
272
#define DA9150_GPADC_CHANNEL_PROCESSED(_id, _hw_id, _type, _ext_name) \
drivers/iio/adc/da9150-gpadc.c
273
DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
drivers/iio/adc/exynos_adc.c
520
#define ADC_CHANNEL(_index, _id) { \
drivers/iio/adc/exynos_adc.c
527
.datasheet_name = _id, \
drivers/iio/adc/lp8788_adc.c
127
#define LP8788_CHAN(_id, _type) { \
drivers/iio/adc/lp8788_adc.c
130
.channel = LPADC_##_id, \
drivers/iio/adc/lp8788_adc.c
133
.datasheet_name = #_id, \
drivers/iio/adc/rockchip_saradc.c
215
#define SARADC_CHANNEL(_index, _id, _res) { \
drivers/iio/adc/rockchip_saradc.c
221
.datasheet_name = _id, \
drivers/interconnect/imx/imx.h
101
#define DEFINE_BUS_MASTER(_name, _id, _dest_id) \
drivers/interconnect/imx/imx.h
102
DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id)
drivers/interconnect/imx/imx.h
104
#define DEFINE_BUS_SLAVE(_name, _id, _adj) \
drivers/interconnect/imx/imx.h
105
DEFINE_BUS_INTERCONNECT(_name, _id, _adj)
drivers/interconnect/imx/imx.h
92
#define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \
drivers/interconnect/imx/imx.h
94
.id = _id, \
drivers/interconnect/qcom/msm8974.c
225
#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
drivers/interconnect/qcom/msm8974.c
229
.id = _id, \
drivers/leds/flash/leds-mt6360.c
39
#define MT6360_REG_FLEDBASE(_id) (0x372 + 4 * (_id - MT6360_LED_FLASH1))
drivers/leds/flash/leds-mt6360.c
40
#define MT6360_REG_FLEDISTRB(_id) (MT6360_REG_FLEDBASE(_id) + 2)
drivers/leds/flash/leds-mt6360.c
41
#define MT6360_REG_FLEDITOR(_id) (MT6360_REG_FLEDBASE(_id) + 3)
drivers/leds/flash/leds-mt6360.c
49
#define MT6360_FLCSEN_MASK(_id) BIT(MT6360_LED_FLASH2 - _id)
drivers/leds/flash/leds-mt6370-flash.c
36
#define MT6370_REG_FLEDISTRB(_id) (0x174 + 4 * (_id))
drivers/leds/flash/leds-mt6370-flash.c
37
#define MT6370_REG_FLEDITOR(_id) (0x175 + 4 * (_id))
drivers/leds/flash/leds-mt6370-flash.c
43
#define MT6370_FLCSEN_MASK(_id) BIT(MT6370_LED_FLASH2 - (_id))
drivers/leds/flash/leds-sy7802.c
39
#define SY7802_LEDS_MASK(_id) (BIT(_id) << SY7802_LEDS_SHIFT)
drivers/leds/flash/leds-sy7802.c
43
#define SY7802_TORCH_CURRENT_MASK(_id) \
drivers/leds/flash/leds-sy7802.c
44
(GENMASK(2, 0) << (SY7802_TORCH_CURRENT_SHIFT * (_id)))
drivers/leds/flash/leds-sy7802.c
49
#define SY7802_FLASH_CURRENT_MASK(_id) \
drivers/leds/flash/leds-sy7802.c
50
(GENMASK(3, 0) << (SY7802_FLASH_CURRENT_SHIFT * (_id)))
drivers/media/platform/microchip/microchip-isc-base.c
1576
#define ISC_CTRL_OFF(_name, _id, _name_str) \
drivers/media/platform/microchip/microchip-isc-base.c
1579
.id = _id, \
drivers/media/platform/microchip/microchip-isc-base.c
1594
#define ISC_CTRL_GAIN(_name, _id, _name_str) \
drivers/media/platform/microchip/microchip-isc-base.c
1597
.id = _id, \
drivers/memory/bt1-l2-ctl.c
73
#define L2_CTL_ATTR_RW(_name, _prefix, _id) \
drivers/memory/bt1-l2-ctl.c
75
{ __ATTR(_name, 0644, _prefix##_show, _prefix##_store), _id }
drivers/memory/mtk-smi.c
84
u32 _id = (id) & 0x3; \
drivers/memory/mtk-smi.c
85
(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
drivers/mfd/lm3533-core.c
314
#define LM3533_OUTPUT_ATTR(_name, _mode, _show, _store, _type, _id) \
drivers/mfd/lm3533-core.c
318
.u.output = { .id = _id }, }
drivers/mfd/lm3533-core.c
320
#define LM3533_OUTPUT_ATTR_RW(_name, _type, _id) \
drivers/mfd/lm3533-core.c
322
show_output, store_output, _type, _id)
drivers/mfd/lp8788.c
24
#define MFD_DEV_WITH_ID(_name, _id) \
drivers/mfd/lp8788.c
27
.id = _id, \
drivers/mfd/rc5t583.c
30
#define DEEPSLEEP_INIT(_id, _reg, _pos) \
drivers/mfd/ti-lmu.c
53
#define LM363X_REGULATOR(_id) \
drivers/mfd/ti-lmu.c
56
.id = _id, \
drivers/net/dsa/mv88e6xxx/chip.c
1407
#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
drivers/net/dsa/mv88e6xxx/chip.c
1409
&mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
drivers/net/dsa/mv88e6xxx/chip.c
1455
#define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
drivers/net/dsa/mv88e6xxx/chip.c
1457
&mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
drivers/net/ethernet/brocade/bna/bna.h
23
#define bna_is_small_rxq(_id) ((_id) & 0x1)
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-devlink.c
6
#define DPAA2_ETH_TRAP_DROP(_id, _group_id) \
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth-devlink.c
7
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
1000
.id = cpu_to_be32(_id), .tlsid = cpu_to_be64(_tlsid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
1236
#define FUN_ADMIN_ADI_WRITE_REQ_INIT(_subop, _attribute, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
1239
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
136
#define FUN_ADMIN_BIND_ENTRY_INIT(_type, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
138
.type = (_type), .id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
254
_subop, _flags, _id, _epsqid, _entry_size_log2, _nentries, _address, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
260
.id = cpu_to_be32(_id), .epsqid = cpu_to_be32(_epsqid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
274
#define FUN_ADMIN_EPCQ_MODIFY_REQ_INIT(_subop, _flags, _id, _headroom) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
277
.id = cpu_to_be32(_id), .headroom = cpu_to_be16(_headroom), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
329
_subop, _flags, _id, _epcqid, _entry_size_log2, _nentries, _address, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
335
.id = cpu_to_be32(_id), .epcqid = cpu_to_be32(_epcqid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
624
#define FUN_ADMIN_PORT_CREATE_REQ_INIT(_subop, _flags, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
627
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
630
#define FUN_ADMIN_PORT_WRITE_REQ_INIT(_subop, _flags, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
633
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
636
#define FUN_ADMIN_PORT_READ_REQ_INIT(_subop, _flags, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
639
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
642
#define FUN_ADMIN_PORT_XCVR_READ_REQ_INIT(_flags, _id, _bank, _page, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
646
.flags = cpu_to_be16(_flags), .id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
773
#define FUN_ADMIN_RSS_CREATE_REQ_INIT(_subop, _flags, _id, _viid, _alg, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
778
.id = cpu_to_be32(_id), .viid = cpu_to_be32(_viid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
800
#define FUN_ADMIN_VI_CREATE_REQ_INIT(_subop, _flags, _id, _portid) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
803
.id = cpu_to_be32(_id), .portid = cpu_to_be32(_portid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
822
#define FUN_ADMIN_ETH_CREATE_REQ_INIT(_subop, _flags, _id, _portid) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
825
.id = cpu_to_be32(_id), .portid = cpu_to_be32(_portid), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
878
#define FUN_ADMIN_SWU_CREATE_REQ_INIT(_subop, _flags, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
881
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
884
#define FUN_ADMIN_SWU_UPGRADE_REQ_INIT(_subop, _flags, _id, _fourcc, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
888
.id = cpu_to_be32(_id), .fourcc = cpu_to_be32(_fourcc), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
892
#define FUN_ADMIN_SWU_UPGRADE_DATA_REQ_INIT(_subop, _flags, _id, _offset, \
drivers/net/ethernet/fungible/funcore/fun_hci.h
896
.id = cpu_to_be32(_id), .offset = cpu_to_be32(_offset), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
958
#define FUN_ADMIN_KTLS_CREATE_REQ_INIT(_subop, _flags, _id) \
drivers/net/ethernet/fungible/funcore/fun_hci.h
961
.id = cpu_to_be32(_id), \
drivers/net/ethernet/fungible/funcore/fun_hci.h
996
#define FUN_ADMIN_KTLS_MODIFY_REQ_INIT(_subop, _flags, _id, _tlsid, _tcp_seq, \
drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c
14
#define MVPP2_DEF_FLOW(_type, _id, _opts, _ri, _ri_mask) \
drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c
17
.flow_id = _id, \
drivers/net/ethernet/marvell/octeontx2/af/mbox.c
550
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
drivers/net/ethernet/marvell/octeontx2/af/mbox.c
554
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
drivers/net/ethernet/marvell/octeontx2/af/mbox.c
558
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
408
#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
17
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
29
req->hdr.id = _id; \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2198
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2199
case _id: { \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2209
_id != MBOX_MSG_DETACH_RESOURCES && \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2210
_id != MBOX_MSG_NIX_TXSCH_FREE && \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2211
_id != MBOX_MSG_VF_FLR) \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2214
rsp->hdr.id = _id; \
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2226
trace_otx2_msg_process(mbox->pdev, _id, err, req->pcifunc); \
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
979
#define M(_name, _id, fn_name, req, rsp) \
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
24
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
36
req->hdr.id = _id; \
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
37
trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req), 0); \
drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
17
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c
29
req->hdr.id = _id; \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
2101
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
905
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
918
req->hdr.id = _id; \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
920
trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req), pcifunc); \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
927
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
973
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
974
case _id: { \
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
984
rsp->hdr.id = _id; \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
134
#define PRESTERA_TRAP_CONTROL(_id, _group_id, _action) \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
135
DEVLINK_TRAP_GENERIC(CONTROL, _action, _id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
139
#define PRESTERA_TRAP_DRIVER_CONTROL(_id, _group_id) \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
140
DEVLINK_TRAP_DRIVER(CONTROL, TRAP, DEVLINK_PRESTERA_TRAP_ID_##_id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
141
DEVLINK_PRESTERA_TRAP_NAME_##_id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
145
#define PRESTERA_TRAP_EXCEPTION(_id, _group_id) \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
146
DEVLINK_TRAP_GENERIC(EXCEPTION, TRAP, _id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
150
#define PRESTERA_TRAP_DRIVER_EXCEPTION(_id, _group_id) \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
151
DEVLINK_TRAP_DRIVER(EXCEPTION, TRAP, DEVLINK_PRESTERA_TRAP_ID_##_id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
152
DEVLINK_PRESTERA_TRAP_NAME_##_id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
156
#define PRESTERA_TRAP_DRIVER_DROP(_id, _group_id) \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
157
DEVLINK_TRAP_DRIVER(DROP, DROP, DEVLINK_PRESTERA_TRAP_ID_##_id, \
drivers/net/ethernet/marvell/prestera/prestera_devlink.c
158
DEVLINK_PRESTERA_TRAP_NAME_##_id, \
drivers/net/ethernet/mediatek/mtk_eth_soc.c
4783
const __be32 *_id = of_get_property(np, "reg", NULL);
drivers/net/ethernet/mediatek/mtk_eth_soc.c
4791
if (!_id) {
drivers/net/ethernet/mediatek/mtk_eth_soc.c
4796
id = be32_to_cpup(_id);
drivers/net/ethernet/mellanox/mlx5/core/devlink.c
955
#define MLX5_TRAP_DROP(_id, _group_id) \
drivers/net/ethernet/mellanox/mlx5/core/devlink.c
956
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/ethernet/mellanox/mlxsw/reg.h
21
#define MLXSW_REG_DEFINE(_name, _id, _len) \
drivers/net/ethernet/mellanox/mlxsw/reg.h
23
.id = _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
382
#define MLXSW_SP_TRAP_DROP(_id, _group_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
383
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
387
#define MLXSW_SP_TRAP_DROP_EXT(_id, _group_id, _metadata) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
388
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
392
#define MLXSW_SP_TRAP_BUFFER_DROP(_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
393
DEVLINK_TRAP_GENERIC(DROP, TRAP, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
397
#define MLXSW_SP_TRAP_DRIVER_DROP(_id, _group_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
398
DEVLINK_TRAP_DRIVER(DROP, DROP, DEVLINK_MLXSW_TRAP_ID_##_id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
399
DEVLINK_MLXSW_TRAP_NAME_##_id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
403
#define MLXSW_SP_TRAP_EXCEPTION(_id, _group_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
404
DEVLINK_TRAP_GENERIC(EXCEPTION, TRAP, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
408
#define MLXSW_SP_TRAP_CONTROL(_id, _group_id, _action) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
409
DEVLINK_TRAP_GENERIC(CONTROL, _action, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
413
#define MLXSW_SP_RXL_DISCARD(_id, _group_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
414
MLXSW_RXL_DIS(mlxsw_sp_rx_drop_listener, DISCARD_##_id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
418
#define MLXSW_SP_RXL_ACL_DISCARD(_id, _en_group_id, _dis_group_id) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
419
MLXSW_RXL_DIS(mlxsw_sp_rx_acl_drop_listener, DISCARD_##_id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
427
#define MLXSW_SP_RXL_EXCEPTION(_id, _group_id, _action) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
428
MLXSW_RXL(mlxsw_sp_rx_mark_listener, _id, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
431
#define MLXSW_SP_RXL_NO_MARK(_id, _group_id, _action, _is_ctrl) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
432
MLXSW_RXL(mlxsw_sp_rx_no_mark_listener, _id, _action, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
435
#define MLXSW_SP_RXL_MARK(_id, _group_id, _action, _is_ctrl) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
436
MLXSW_RXL(mlxsw_sp_rx_mark_listener, _id, _action, _is_ctrl, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
439
#define MLXSW_SP_RXL_L3_MARK(_id, _group_id, _action, _is_ctrl) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
440
MLXSW_RXL(mlxsw_sp_rx_l3_mark_listener, _id, _action, _is_ctrl, \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
443
#define MLXSW_SP_TRAP_POLICER(_id, _rate, _burst) \
drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c
444
DEVLINK_TRAP_POLICER(_id, _rate, _burst, \
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
149
#define fta_get_uint(_results, _id) \
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
150
fbnic_tlv_attr_get_unsigned(_results[_id], 0)
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
151
#define fta_get_sint(_results, _id) \
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
152
fbnic_tlv_attr_get_signed(_results[_id], 0)
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
153
#define fta_get_str(_results, _id, _dst, _dstsize) \
drivers/net/ethernet/meta/fbnic/fbnic_tlv.h
154
fbnic_tlv_attr_get_string(_results[_id], _dst, _dstsize)
drivers/net/ethernet/sfc/mae.c
313
#define TABLE_FIND_KEY(_desc, _id) \
drivers/net/ethernet/sfc/mae.c
314
efx_mae_table_hook_find((_desc)->n_keys, (_desc)->keys, _id)
drivers/net/ethernet/sfc/mae.c
315
#define TABLE_FIND_RESP(_desc, _id) \
drivers/net/ethernet/sfc/mae.c
316
efx_mae_table_hook_find((_desc)->n_resps, (_desc)->resps, _id)
drivers/net/netdevsim/dev.c
741
#define NSIM_TRAP_DROP(_id, _group_id) \
drivers/net/netdevsim/dev.c
742
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/netdevsim/dev.c
745
#define NSIM_TRAP_DROP_EXT(_id, _group_id, _metadata) \
drivers/net/netdevsim/dev.c
746
DEVLINK_TRAP_GENERIC(DROP, DROP, _id, \
drivers/net/netdevsim/dev.c
749
#define NSIM_TRAP_EXCEPTION(_id, _group_id) \
drivers/net/netdevsim/dev.c
750
DEVLINK_TRAP_GENERIC(EXCEPTION, TRAP, _id, \
drivers/net/netdevsim/dev.c
753
#define NSIM_TRAP_CONTROL(_id, _group_id, _action) \
drivers/net/netdevsim/dev.c
754
DEVLINK_TRAP_GENERIC(CONTROL, _action, _id, \
drivers/net/netdevsim/dev.c
757
#define NSIM_TRAP_DRIVER_EXCEPTION(_id, _group_id) \
drivers/net/netdevsim/dev.c
758
DEVLINK_TRAP_DRIVER(EXCEPTION, TRAP, NSIM_TRAP_ID_##_id, \
drivers/net/netdevsim/dev.c
759
NSIM_TRAP_NAME_##_id, \
drivers/net/netdevsim/dev.c
768
#define NSIM_TRAP_POLICER(_id, _rate, _burst) \
drivers/net/netdevsim/dev.c
769
DEVLINK_TRAP_POLICER(_id, _rate, _burst, \
drivers/net/phy/dp83822.c
1175
#define DP83822_PHY_DRIVER(_id, _name) \
drivers/net/phy/dp83822.c
1177
PHY_ID_MATCH_MODEL(_id), \
drivers/net/phy/dp83822.c
1196
#define DP83825_PHY_DRIVER(_id, _name) \
drivers/net/phy/dp83822.c
1198
PHY_ID_MATCH_MODEL(_id), \
drivers/net/phy/dp83822.c
1212
#define DP83826_PHY_DRIVER(_id, _name) \
drivers/net/phy/dp83822.c
1214
PHY_ID_MATCH_MODEL(_id), \
drivers/net/phy/dp83848.c
135
#define DP83848_PHY_DRIVER(_id, _name, _config_init) \
drivers/net/phy/dp83848.c
137
.phy_id = _id, \
drivers/net/phy/dp83869.c
904
#define DP83869_PHY_DRIVER(_id, _name) \
drivers/net/phy/dp83869.c
906
PHY_ID_MATCH_MODEL(_id), \
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.h
21
#define BRCMF_ABSTRACT_ENUM_DEF(_id, _val) \
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fweh.h
22
BRCMF_ENUM_DEF(_id, (BRCMF_ABSTRACT_EVENT_BIT | (_val)))
drivers/net/wireless/intel/iwlwifi/fw/api/context.h
30
#define FW_CMD_ID_AND_COLOR(_id, _color) (((_id) << FW_CTXT_ID_POS) |\
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2215
#define BT_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) }
drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
593
#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
594
MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \
drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
595
MT_TX_AGG_CNT_BASE1 + (((_id) - 8) << 2))
drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
52
#define GROUP_5G(_id) \
drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
53
MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
54
MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
55
MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
56
MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
drivers/net/wireless/mediatek/mt76/mt7915/regs.h
475
#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
drivers/net/wireless/mediatek/mt76/mt7915/regs.h
476
FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
drivers/net/wireless/mediatek/mt76/mt792x_regs.h
172
#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
drivers/net/wireless/mediatek/mt76/mt792x_regs.h
173
FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
drivers/net/wireless/mediatek/mt76/mt7996/regs.h
339
#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
drivers/net/wireless/mediatek/mt76/mt7996/regs.h
340
FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
drivers/net/wireless/mediatek/mt76/mt7996/regs.h
41
#define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)])
drivers/net/wireless/mediatek/mt7601u/regs.h
527
#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
drivers/net/wireless/mediatek/mt7601u/regs.h
528
MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \
drivers/net/wireless/mediatek/mt7601u/regs.h
529
MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2))
drivers/net/wireless/realtek/rtlwifi/base.c
1234
({typeof(rate_id) _id = rate_id; \
drivers/net/wireless/realtek/rtlwifi/base.c
1236
rtl_mrate_idx_to_arfr_id(hw, _id, \
drivers/net/wireless/realtek/rtlwifi/base.c
1239
_id); })
drivers/net/wireless/realtek/rtlwifi/base.c
778
({typeof(rate_id) _id = rate_id; \
drivers/net/wireless/realtek/rtlwifi/base.c
780
rtl_mrate_idx_to_arfr_id(hw, _id, \
drivers/net/wireless/realtek/rtlwifi/base.c
783
_id); })
drivers/net/wireless/realtek/rtw88/sdio.h
134
#define RTW_SDIO_ADDR_RX_RX0FF_GEN(_id) (0x0e000 | ((_id) & 0x3))
drivers/pci/endpoint/functions/pci-epf-test.c
1323
#define PCI_EPF_TEST_BAR_SIZE_R(_name, _id) \
drivers/pci/endpoint/functions/pci-epf-test.c
1331
return sysfs_emit(page, "%zu\n", epf_test->bar_size[_id]); \
drivers/pci/endpoint/functions/pci-epf-test.c
1334
#define PCI_EPF_TEST_BAR_SIZE_W(_name, _id) \
drivers/pci/endpoint/functions/pci-epf-test.c
1358
epf_test->bar_size[_id] = val; \
drivers/pci/endpoint/functions/pci-epf-vntb.c
1039
#define EPF_NTB_BAR_R(_name, _id) \
drivers/pci/endpoint/functions/pci-epf-vntb.c
1046
return sprintf(page, "%d\n", ntb->epf_ntb_bar[_id]); \
drivers/pci/endpoint/functions/pci-epf-vntb.c
1049
#define EPF_NTB_BAR_W(_name, _id) \
drivers/pci/endpoint/functions/pci-epf-vntb.c
1065
ntb->epf_ntb_bar[_id] = val; \
drivers/perf/amlogic/meson_ddr_pmu_core.c
234
#define AML_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/amlogic/meson_ddr_pmu_core.c
237
.id = _id, \
drivers/perf/fsl_imx8_ddr_perf.c
265
#define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/fsl_imx8_ddr_perf.c
266
PMU_EVENT_ATTR_ID(_name, ddr_pmu_event_show, _id)
drivers/perf/fsl_imx9_ddr_perf.c
195
#define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \
drivers/perf/fsl_imx9_ddr_perf.c
198
.id = _id, \
drivers/perf/fsl_imx9_ddr_perf.c
202
#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/fsl_imx9_ddr_perf.c
203
DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL)
drivers/perf/fsl_imx9_ddr_perf.c
205
#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/fsl_imx9_ddr_perf.c
206
DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
drivers/perf/fsl_imx9_ddr_perf.c
208
#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/fsl_imx9_ddr_perf.c
209
DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data)
drivers/perf/fujitsu_uncore_pmu.c
318
#define MAC_EVENT_ATTR(_name, _id) \
drivers/perf/fujitsu_uncore_pmu.c
319
PMU_EVENT_ATTR_ID(_name, fujitsu_uncore_pmu_event_show, _id)
drivers/perf/fujitsu_uncore_pmu.c
344
#define PCI_EVENT_ATTR(_name, _id) \
drivers/perf/fujitsu_uncore_pmu.c
345
PMU_EVENT_ATTR_ID(_name, fujitsu_uncore_pmu_event_show, _id)
drivers/perf/hisilicon/hisi_pcie_pmu.c
117
#define HISI_PCIE_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/hisilicon/hisi_pcie_pmu.c
118
PMU_EVENT_ATTR_ID(_name, hisi_pcie_event_sysfs_show, _id)
drivers/perf/marvell_cn10k_ddr_pmu.c
201
#define CN10K_DDR_PMU_EVENT_ATTR(_name, _id) \
drivers/perf/marvell_cn10k_ddr_pmu.c
202
PMU_EVENT_ATTR_ID(_name, cn10k_ddr_pmu_event_show, _id)
drivers/perf/marvell_pem_pmu.c
106
#define PEM_EVENT_ATTR(_name, _id) \
drivers/perf/marvell_pem_pmu.c
109
.id = _id, } \
drivers/perf/qcom_l2_pmu.c
682
#define L2CACHE_EVENT_ATTR(_name, _id) \
drivers/perf/qcom_l2_pmu.c
683
PMU_EVENT_ATTR_ID(_name, l2cache_pmu_event_show, _id)
drivers/perf/qcom_l3_pmu.c
640
#define L3CACHE_EVENT_ATTR(_name, _id) \
drivers/perf/qcom_l3_pmu.c
641
PMU_EVENT_ATTR_ID(_name, l3cache_pmu_event_show, _id)
drivers/perf/starfive_starlink_pmu.c
59
#define STARLINK_EVENT_ATTR(_name, _id) \
drivers/perf/starfive_starlink_pmu.c
60
PMU_EVENT_ATTR_ID(_name, starlink_pmu_sysfs_event_show, _id)
drivers/pinctrl/mvebu/pinctrl-mvebu.h
177
#define MPP_MODE(_id, ...) \
drivers/pinctrl/mvebu/pinctrl-mvebu.h
179
.pid = _id, \
drivers/pinctrl/mvebu/pinctrl-mvebu.h
184
#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
drivers/pinctrl/mvebu/pinctrl-mvebu.h
187
.id = _id, \
drivers/pinctrl/pinctrl-mlxbf3.c
34
#define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
drivers/pinctrl/pinctrl-mlxbf3.c
37
.id = _id, \
drivers/pinctrl/pinctrl-palmas.c
433
#define PIN_INFO(_name, _id, _pud_info, _od_info) \
drivers/pinctrl/pinctrl-palmas.c
435
.mux_opt = PALMAS_PINMUX_##_id, \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
107
#define CV1800_GENERATE_PIN_MUX2(_id, _power_domain, _type, \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
114
.id = (_id), \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
72
#define CV1800_FUNC_PIN(_id, _power_domain, _type, \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
76
.id = (_id), \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
87
#define CV1800_GENERAL_PIN(_id, _power_domain, _type, \
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
92
.id = (_id), \
drivers/pinctrl/sophgo/pinctrl-sg2042.h
34
#define SG2042_GENERAL_PIN(_id, _offset, _flag) \
drivers/pinctrl/sophgo/pinctrl-sg2042.h
37
.id = (_id), \
drivers/pinctrl/spacemit/pinctrl-k1.h
33
#define K1_FUNC_PIN(_id, _gpiofunc, _io) \
drivers/pinctrl/spacemit/pinctrl-k1.h
35
.pin = (_id), \
drivers/pmdomain/marvell/pxa1908-power-controller.c
126
#define DOMAIN(_id, _name, ctrl, mode, state) \
drivers/pmdomain/marvell/pxa1908-power-controller.c
127
[_id] = { \
drivers/pmdomain/marvell/pxa1908-power-controller.c
132
.id = _id, \
drivers/regulator/88pm8607.c
270
#define PM8607_LDO(_id, vreg, shift, ereg, ebit) \
drivers/regulator/88pm8607.c
273
.name = "LDO" #_id, \
drivers/regulator/88pm8607.c
274
.of_match = of_match_ptr("LDO" #_id), \
drivers/regulator/88pm8607.c
278
.id = PM8607_ID_LDO##_id, \
drivers/regulator/88pm8607.c
280
.volt_table = LDO##_id##_table, \
drivers/regulator/88pm8607.c
281
.n_voltages = ARRAY_SIZE(LDO##_id##_table), \
drivers/regulator/88pm8607.c
283
.vsel_mask = (ARRAY_SIZE(LDO##_id##_table) - 1) << (shift), \
drivers/regulator/88pm8607.c
288
.vol_suspend = (unsigned int *)&LDO##_id##_suspend_table, \
drivers/regulator/ab8500.c
1158
#define REG_INIT(_id, _bank, _addr, _mask) \
drivers/regulator/ab8500.c
1159
[_id] = { \
drivers/regulator/act8865-regulator.c
437
#define ACT88xx_REG_(_name, _family, _id, _vsel_reg, _supply, _ops) \
drivers/regulator/act8865-regulator.c
438
[_family##_ID_##_id] = { \
drivers/regulator/act8865-regulator.c
444
.id = _family##_ID_##_id, \
drivers/regulator/act8865-regulator.c
450
.vsel_reg = _family##_##_id##_##_vsel_reg, \
drivers/regulator/act8865-regulator.c
452
.enable_reg = _family##_##_id##_CTRL, \
drivers/regulator/act8865-regulator.c
454
.pull_down_reg = _family##_##_id##_CTRL, \
drivers/regulator/act8865-regulator.c
459
#define ACT88xx_REG(_name, _family, _id, _vsel_reg, _supply) \
drivers/regulator/act8865-regulator.c
460
ACT88xx_REG_(_name, _family, _id, _vsel_reg, _supply, &act8865_ops)
drivers/regulator/act8865-regulator.c
462
#define ACT88xx_LDO(_name, _family, _id, _vsel_reg, _supply) \
drivers/regulator/act8865-regulator.c
463
ACT88xx_REG_(_name, _family, _id, _vsel_reg, _supply, &act8865_ldo_ops)
drivers/regulator/act8945a-regulator.c
234
#define ACT89xx_REG(_name, _family, _id, _vsel_reg, _supply) \
drivers/regulator/act8945a-regulator.c
235
[_family##_ID_##_id] = { \
drivers/regulator/act8945a-regulator.c
238
.of_match = of_match_ptr("REG_"#_id), \
drivers/regulator/act8945a-regulator.c
241
.id = _family##_ID_##_id, \
drivers/regulator/act8945a-regulator.c
247
.vsel_reg = _family##_##_id##_##_vsel_reg, \
drivers/regulator/act8945a-regulator.c
249
.enable_reg = _family##_##_id##_CTRL, \
drivers/regulator/adp5055-regulator.c
313
#define ADP5055_REG_(_name, _id, _ch, _ops) \
drivers/regulator/adp5055-regulator.c
314
[_id] = { \
drivers/regulator/adp5055-regulator.c
318
.id = _id, \
drivers/regulator/adp5055-regulator.c
326
.active_discharge_on = ADP5055_MASK_DIS##_id, \
drivers/regulator/adp5055-regulator.c
328
.active_discharge_mask = ADP5055_MASK_DIS##_id, \
drivers/regulator/adp5055-regulator.c
337
#define ADP5055_REG(_name, _id, _ch) \
drivers/regulator/adp5055-regulator.c
338
ADP5055_REG_(_name, _id, _ch, &adp5055_ops)
drivers/regulator/as3711-regulator.c
122
#define AS3711_REG(_id, _en_reg, _en_bit, _vmask, _sfx) \
drivers/regulator/as3711-regulator.c
123
[AS3711_REGULATOR_ ## _id] = { \
drivers/regulator/as3711-regulator.c
124
.name = "as3711-regulator-" # _id, \
drivers/regulator/as3711-regulator.c
125
.id = AS3711_REGULATOR_ ## _id, \
drivers/regulator/as3711-regulator.c
130
.vsel_reg = AS3711_ ## _id ## _VOLTAGE, \
drivers/regulator/aw37503-regulator.c
133
#define AW37503_REGULATOR_DESC(_id, _name) \
drivers/regulator/aw37503-regulator.c
134
[AW37503_REGULATOR_ID_##_id] = { \
drivers/regulator/aw37503-regulator.c
137
.id = AW37503_REGULATOR_ID_##_id, \
drivers/regulator/aw37503-regulator.c
146
.vsel_reg = AW37503_REG_##_id, \
drivers/regulator/aw37503-regulator.c
148
.active_discharge_on = AW37503_REG_APPS_DIS_##_id, \
drivers/regulator/aw37503-regulator.c
149
.active_discharge_mask = AW37503_REG_APPS_DIS_##_id, \
drivers/regulator/axp20x-regulator.c
352
#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/axp20x-regulator.c
354
[_family##_##_id] = { \
drivers/regulator/axp20x-regulator.c
360
.id = _family##_##_id, \
drivers/regulator/axp20x-regulator.c
374
#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/axp20x-regulator.c
376
[_family##_##_id] = { \
drivers/regulator/axp20x-regulator.c
382
.id = _family##_##_id, \
drivers/regulator/axp20x-regulator.c
394
#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
drivers/regulator/axp20x-regulator.c
395
[_family##_##_id] = { \
drivers/regulator/axp20x-regulator.c
401
.id = _family##_##_id, \
drivers/regulator/axp20x-regulator.c
408
#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
drivers/regulator/axp20x-regulator.c
409
[_family##_##_id] = { \
drivers/regulator/axp20x-regulator.c
415
.id = _family##_##_id, \
drivers/regulator/axp20x-regulator.c
422
#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \
drivers/regulator/axp20x-regulator.c
424
[_family##_##_id] = { \
drivers/regulator/axp20x-regulator.c
430
.id = _family##_##_id, \
drivers/regulator/axp20x-regulator.c
443
#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
drivers/regulator/axp20x-regulator.c
445
AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
drivers/regulator/bd71815-regulator.c
407
#define BD71815_FIXED_REG(_name, _id, ereg, emsk, voltage, _dvs) \
drivers/regulator/bd71815-regulator.c
408
[(_id)] = { \
drivers/regulator/bd71815-regulator.c
416
.id = (_id), \
drivers/regulator/bd71815-regulator.c
426
#define BD71815_BUCK_REG(_name, _id, vsel, ereg, min, max, step, _dvs) \
drivers/regulator/bd71815-regulator.c
427
[(_id)] = { \
drivers/regulator/bd71815-regulator.c
435
.id = (_id), \
drivers/regulator/bd71815-regulator.c
448
#define BD71815_BUCK12_REG(_name, _id, vsel, ereg, min, max, step, \
drivers/regulator/bd71815-regulator.c
450
[(_id)] = { \
drivers/regulator/bd71815-regulator.c
458
.id = (_id), \
drivers/regulator/bd71815-regulator.c
475
#define BD71815_LED_REG(_name, _id, csel, mask, ereg, emsk, currents) \
drivers/regulator/bd71815-regulator.c
476
[(_id)] = { \
drivers/regulator/bd71815-regulator.c
484
.id = (_id), \
drivers/regulator/bd71815-regulator.c
494
#define BD71815_LDO_REG(_name, _id, vsel, ereg, emsk, min, max, step, \
drivers/regulator/bd71815-regulator.c
496
[(_id)] = { \
drivers/regulator/bd71815-regulator.c
504
.id = (_id), \
drivers/regulator/bd9571mwv-regulator.c
35
#define BD9571MWV_REG(_name, _of, _id, _ops, _vr, _vm, _nv, _min, _step, _lmin)\
drivers/regulator/bd9571mwv-regulator.c
40
.id = _id, \
drivers/regulator/da903x-regulator.c
309
#define DA903x_LDO(_pmic, _id, min, max, step, vreg, shift, nbits, ereg, ebit) \
drivers/regulator/da903x-regulator.c
312
.name = "LDO" #_id, \
drivers/regulator/da903x-regulator.c
315
.id = _pmic##_ID_LDO##_id, \
drivers/regulator/da903x-regulator.c
329
#define DA903x_DVC(_pmic, _id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \
drivers/regulator/da903x-regulator.c
332
.name = #_id, \
drivers/regulator/da903x-regulator.c
335
.id = _pmic##_ID_##_id, \
drivers/regulator/da903x-regulator.c
351
#define DA9034_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \
drivers/regulator/da903x-regulator.c
352
DA903x_LDO(DA9034, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
drivers/regulator/da903x-regulator.c
354
#define DA9030_LDO(_id, min, max, step, vreg, shift, nbits, ereg, ebit) \
drivers/regulator/da903x-regulator.c
355
DA903x_LDO(DA9030, _id, min, max, step, vreg, shift, nbits, ereg, ebit)
drivers/regulator/da903x-regulator.c
357
#define DA9030_DVC(_id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \
drivers/regulator/da903x-regulator.c
358
DA903x_DVC(DA9030, _id, min, max, step, vreg, nbits, ureg, ubit, \
drivers/regulator/da903x-regulator.c
361
#define DA9034_DVC(_id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \
drivers/regulator/da903x-regulator.c
362
DA903x_DVC(DA9034, _id, min, max, step, vreg, nbits, ureg, ubit, \
drivers/regulator/da903x-regulator.c
365
#define DA9035_DVC(_id, min, max, step, vreg, nbits, ureg, ubit, ereg, ebit) \
drivers/regulator/da903x-regulator.c
366
DA903x_DVC(DA9035, _id, min, max, step, vreg, nbits, ureg, ubit, \
drivers/regulator/da9052-regulator.c
286
#define DA9052_LDO(_id, _name, step, min, max, sbits, ebits, abits) \
drivers/regulator/da9052-regulator.c
294
.id = DA9052_ID_##_id,\
drivers/regulator/da9052-regulator.c
297
.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
drivers/regulator/da9052-regulator.c
299
.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
drivers/regulator/da9052-regulator.c
308
#define DA9052_DCDC(_id, _name, step, min, max, sbits, ebits, abits) \
drivers/regulator/da9052-regulator.c
316
.id = DA9052_ID_##_id,\
drivers/regulator/da9052-regulator.c
319
.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
drivers/regulator/da9052-regulator.c
321
.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
drivers/regulator/da9055-regulator.c
330
#define DA9055_LDO(_id, step, min, max, vbits, voffset) \
drivers/regulator/da9055-regulator.c
333
.name = #_id,\
drivers/regulator/da9055-regulator.c
334
.of_match = of_match_ptr(#_id),\
drivers/regulator/da9055-regulator.c
338
.id = DA9055_ID_##_id,\
drivers/regulator/da9055-regulator.c
340
.enable_reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
348
.reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
353
.reg_a = DA9055_REG_VBCORE_A + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
354
.reg_b = DA9055_REG_VBCORE_B + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
360
#define DA9055_BUCK(_id, step, min, max, vbits, voffset, mbits, sbits) \
drivers/regulator/da9055-regulator.c
363
.name = #_id,\
drivers/regulator/da9055-regulator.c
364
.of_match = of_match_ptr(#_id),\
drivers/regulator/da9055-regulator.c
368
.id = DA9055_ID_##_id,\
drivers/regulator/da9055-regulator.c
370
.enable_reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
382
.reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
387
.reg_a = DA9055_REG_VBCORE_A + DA9055_ID_##_id, \
drivers/regulator/da9055-regulator.c
388
.reg_b = DA9055_REG_VBCORE_B + DA9055_ID_##_id, \
drivers/regulator/da9211-regulator.c
250
#define DA9211_BUCK(_id) \
drivers/regulator/da9211-regulator.c
252
.name = #_id,\
drivers/regulator/da9211-regulator.c
255
.id = DA9211_ID_##_id,\
drivers/regulator/da9211-regulator.c
259
.enable_reg = DA9211_REG_BUCKA_CONT + DA9211_ID_##_id,\
drivers/regulator/da9211-regulator.c
261
.vsel_reg = DA9211_REG_VBUCKA_A + DA9211_ID_##_id * 2,\
drivers/regulator/hi6421-regulator.c
129
#define HI6421_LDO(_id, _match, v_table, vreg, vmask, ereg, emask, \
drivers/regulator/hi6421-regulator.c
131
[HI6421_##_id] = { \
drivers/regulator/hi6421-regulator.c
133
.name = #_id, \
drivers/regulator/hi6421-regulator.c
138
.id = HI6421_##_id, \
drivers/regulator/hi6421-regulator.c
168
#define HI6421_LDO_LINEAR(_id, _match, _min_uV, n_volt, vstep, vreg, vmask,\
drivers/regulator/hi6421-regulator.c
170
[HI6421_##_id] = { \
drivers/regulator/hi6421-regulator.c
172
.name = #_id, \
drivers/regulator/hi6421-regulator.c
177
.id = HI6421_##_id, \
drivers/regulator/hi6421-regulator.c
208
#define HI6421_LDO_LINEAR_RANGE(_id, _match, n_volt, volt_ranges, vreg, vmask,\
drivers/regulator/hi6421-regulator.c
210
[HI6421_##_id] = { \
drivers/regulator/hi6421-regulator.c
212
.name = #_id, \
drivers/regulator/hi6421-regulator.c
217
.id = HI6421_##_id, \
drivers/regulator/hi6421-regulator.c
245
#define HI6421_BUCK012(_id, _match, vreg, vmask, ereg, emask, sleepmask,\
drivers/regulator/hi6421-regulator.c
247
[HI6421_##_id] = { \
drivers/regulator/hi6421-regulator.c
249
.name = #_id, \
drivers/regulator/hi6421-regulator.c
254
.id = HI6421_##_id, \
drivers/regulator/hi6421-regulator.c
282
#define HI6421_BUCK345(_id, _match, v_table, vreg, vmask, ereg, emask, \
drivers/regulator/hi6421-regulator.c
284
[HI6421_##_id] = { \
drivers/regulator/hi6421-regulator.c
286
.name = #_id, \
drivers/regulator/hi6421-regulator.c
291
.id = HI6421_##_id, \
drivers/regulator/hi6421v600-regulator.c
74
#define HI6421V600_LDO(_id, vtable, ereg, emask, vreg, \
drivers/regulator/hi6421v600-regulator.c
76
[hi6421v600_##_id] = { \
drivers/regulator/hi6421v600-regulator.c
78
.name = #_id, \
drivers/regulator/hi6421v600-regulator.c
79
.of_match = of_match_ptr(#_id), \
drivers/regulator/hi6421v600-regulator.c
83
.id = hi6421v600_##_id, \
drivers/regulator/lp873x-regulator.c
15
#define LP873X_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm, _er, _em, \
drivers/regulator/lp873x-regulator.c
17
[_id] = { \
drivers/regulator/lp873x-regulator.c
21
.id = _id, \
drivers/regulator/lp8755.c
156
#define lp8755_rail(_id) "lp8755_buck"#_id
drivers/regulator/lp8755.c
157
#define lp8755_buck_init(_id)\
drivers/regulator/lp8755.c
160
.name = lp8755_rail(_id),\
drivers/regulator/lp8755.c
214
#define lp8755_buck_desc(_id)\
drivers/regulator/lp8755.c
216
.name = lp8755_rail(_id),\
drivers/regulator/lp8755.c
217
.id = LP8755_BUCK##_id,\
drivers/regulator/lp8755.c
224
.enable_reg = LP8755_REG_BUCK##_id,\
drivers/regulator/lp8755.c
226
.vsel_reg = LP8755_REG_BUCK##_id,\
drivers/regulator/lp8755.c
228
.ramp_reg = (LP8755_BUCK##_id) + 0x7,\
drivers/regulator/lp87565-regulator.c
26
#define LP87565_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm, \
drivers/regulator/lp87565-regulator.c
28
[_id] = { \
drivers/regulator/lp87565-regulator.c
32
.id = _id, \
drivers/regulator/ltc3676.c
195
#define LTC3676_REG(_id, _name, _ops, en_reg, en_bit, dvba_reg, dvb_mask) \
drivers/regulator/ltc3676.c
196
[LTC3676_ ## _id] = { \
drivers/regulator/ltc3676.c
208
.id = LTC3676_ ## _id, \
drivers/regulator/ltc3676.c
216
#define LTC3676_LINEAR_REG(_id, _name, _en, _dvba) \
drivers/regulator/ltc3676.c
217
LTC3676_REG(_id, _name, linear, \
drivers/regulator/ltc3676.c
221
#define LTC3676_FIXED_REG(_id, _name, _en_reg, _en_bit) \
drivers/regulator/ltc3676.c
222
LTC3676_REG(_id, _name, fixed, LTC3676_ ## _en_reg, _en_bit, 0, 0)
drivers/regulator/max77541-regulator.c
55
#define MAX77540_BUCK(_id, _ops) \
drivers/regulator/max77541-regulator.c
56
{ .id = MAX77541_BUCK ## _id, \
drivers/regulator/max77541-regulator.c
57
.name = "buck"#_id, \
drivers/regulator/max77541-regulator.c
58
.of_match = "buck"#_id, \
drivers/regulator/max77541-regulator.c
61
.enable_mask = MAX77541_BIT_M ## _id ## _EN, \
drivers/regulator/max77541-regulator.c
66
.vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
drivers/regulator/max77541-regulator.c
68
.vsel_range_reg = MAX77541_REG_M ## _id ## _CFG1, \
drivers/regulator/max77541-regulator.c
74
#define MAX77541_BUCK(_id, _ops) \
drivers/regulator/max77541-regulator.c
75
{ .id = MAX77541_BUCK ## _id, \
drivers/regulator/max77541-regulator.c
76
.name = "buck"#_id, \
drivers/regulator/max77541-regulator.c
77
.of_match = "buck"#_id, \
drivers/regulator/max77541-regulator.c
80
.enable_mask = MAX77541_BIT_M ## _id ## _EN, \
drivers/regulator/max77541-regulator.c
85
.vsel_reg = MAX77541_REG_M ## _id ## _VOUT, \
drivers/regulator/max77541-regulator.c
87
.vsel_range_reg = MAX77541_REG_M ## _id ## _CFG1, \
drivers/regulator/max77620-regulator.c
660
#define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
drivers/regulator/max77620-regulator.c
662
[MAX77620_REGULATOR_ID_##_id] = { \
drivers/regulator/max77620-regulator.c
664
.volt_addr = MAX77620_REG_##_id, \
drivers/regulator/max77620-regulator.c
665
.cfg_addr = MAX77620_REG_##_id##_CFG, \
drivers/regulator/max77620-regulator.c
666
.fps_addr = MAX77620_REG_FPS_##_id, \
drivers/regulator/max77620-regulator.c
677
.id = MAX77620_REGULATOR_ID_##_id, \
drivers/regulator/max77620-regulator.c
684
.vsel_reg = MAX77620_REG_##_id, \
drivers/regulator/max77620-regulator.c
688
.active_discharge_reg = MAX77620_REG_##_id##_CFG, \
drivers/regulator/max77620-regulator.c
694
#define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
drivers/regulator/max77620-regulator.c
695
[MAX77620_REGULATOR_ID_##_id] = { \
drivers/regulator/max77620-regulator.c
697
.volt_addr = MAX77620_REG_##_id##_CFG, \
drivers/regulator/max77620-regulator.c
698
.cfg_addr = MAX77620_REG_##_id##_CFG2, \
drivers/regulator/max77620-regulator.c
699
.fps_addr = MAX77620_REG_FPS_##_id, \
drivers/regulator/max77620-regulator.c
709
.id = MAX77620_REGULATOR_ID_##_id, \
drivers/regulator/max77620-regulator.c
716
.vsel_reg = MAX77620_REG_##_id##_CFG, \
drivers/regulator/max77620-regulator.c
720
.active_discharge_reg = MAX77620_REG_##_id##_CFG2, \
drivers/regulator/max77826-regulator.c
118
#define MAX77826_LDO(_id, _type) \
drivers/regulator/max77826-regulator.c
119
[MAX77826_LDO ## _id] = { \
drivers/regulator/max77826-regulator.c
120
.id = MAX77826_LDO ## _id, \
drivers/regulator/max77826-regulator.c
121
.name = "LDO"#_id, \
drivers/regulator/max77826-regulator.c
122
.of_match = of_match_ptr("LDO"#_id), \
drivers/regulator/max77826-regulator.c
128
.enable_reg = MAX77826_REG_LDO_OPMD1 + (_id - 1) / 4, \
drivers/regulator/max77826-regulator.c
129
.enable_mask = BIT(((_id - 1) % 4) * 2 + 1), \
drivers/regulator/max77826-regulator.c
130
.vsel_reg = MAX77826_REG_LDO1_CFG + (_id - 1), \
drivers/regulator/max77826-regulator.c
135
#define MAX77826_BUCK(_idx, _id, _ops) \
drivers/regulator/max77826-regulator.c
136
[MAX77826_ ## _id] = { \
drivers/regulator/max77826-regulator.c
137
.id = MAX77826_ ## _id, \
drivers/regulator/max77826-regulator.c
138
.name = #_id, \
drivers/regulator/max77826-regulator.c
139
.of_match = of_match_ptr(#_id), \
drivers/regulator/max77826-regulator.c
142
.min_uV = MAX77826_ ## _id ## _VOLT_MIN, \
drivers/regulator/max77826-regulator.c
143
.uV_step = MAX77826_ ## _id ## _VOLT_STEP, \
drivers/regulator/max77826-regulator.c
144
.n_voltages = MAX77826_VOLT_RANGE(_id), \
drivers/regulator/max77826-regulator.c
148
.vsel_mask = MAX77826_MASK_ ## _id, \
drivers/regulator/max77838-regulator.c
73
#define MAX77838_LDO(_id) \
drivers/regulator/max77838-regulator.c
74
[MAX77838_LDO ## _id] = { \
drivers/regulator/max77838-regulator.c
75
.id = MAX77838_LDO ## _id, \
drivers/regulator/max77838-regulator.c
76
.name = "ldo"#_id, \
drivers/regulator/max77838-regulator.c
77
.of_match = of_match_ptr("ldo"#_id), \
drivers/regulator/max77838-regulator.c
84
.enable_mask = MAX77838_LDO ## _id ## _EN, \
drivers/regulator/max77838-regulator.c
85
.vsel_reg = MAX77838_REG_LDO ## _id ## _CFG, \
drivers/regulator/max77838-regulator.c
90
.active_discharge_reg = MAX77838_REG_LDO ## _id ## _CFG, \
drivers/regulator/max8907-regulator.c
183
#define MATCH(_name, _id) \
drivers/regulator/max8907-regulator.c
184
[MAX8907_##_id] = { \
drivers/regulator/max8907-regulator.c
186
.driver_data = (void *)&max8907_regulators[MAX8907_##_id], \
drivers/regulator/max8925-regulator.c
155
#define MAX8925_SDV(_id, min, max, step) \
drivers/regulator/max8925-regulator.c
158
.name = "SDV" #_id, \
drivers/regulator/max8925-regulator.c
159
.of_match = of_match_ptr("SDV" #_id), \
drivers/regulator/max8925-regulator.c
163
.id = MAX8925_ID_SD##_id, \
drivers/regulator/max8925-regulator.c
169
.vol_reg = MAX8925_SDV##_id, \
drivers/regulator/max8925-regulator.c
170
.enable_reg = MAX8925_SDCTL##_id, \
drivers/regulator/max8925-regulator.c
173
#define MAX8925_LDO(_id, min, max, step) \
drivers/regulator/max8925-regulator.c
176
.name = "LDO" #_id, \
drivers/regulator/max8925-regulator.c
177
.of_match = of_match_ptr("LDO" #_id), \
drivers/regulator/max8925-regulator.c
181
.id = MAX8925_ID_LDO##_id, \
drivers/regulator/max8925-regulator.c
187
.vol_reg = MAX8925_LDOVOUT##_id, \
drivers/regulator/max8925-regulator.c
188
.enable_reg = MAX8925_LDOCTL##_id, \
drivers/regulator/max8998.c
504
#define MAX8998_OTHERS_REG(_name, _id) \
drivers/regulator/max8998.c
507
.id = _id, \
drivers/regulator/mcp16502.c
110
#define MCP16502_REGULATOR(_name, _id, _sn, _ranges, _ops, _ramp_table) \
drivers/regulator/mcp16502.c
111
[_id] = { \
drivers/regulator/mcp16502.c
115
.id = _id, \
drivers/regulator/mcp16502.c
125
.vsel_reg = (((_id) + 1) << 4), \
drivers/regulator/mcp16502.c
127
.enable_reg = (((_id) + 1) << 4), \
drivers/regulator/mcp16502.c
129
.ramp_reg = MCP16502_REG_BASE(_id, CFG), \
drivers/regulator/mp5416.c
52
#define MP5416BUCK(_name, _id, _ilim, _dreg, _dval, _vsel) \
drivers/regulator/mp5416.c
53
[MP5416_BUCK ## _id] = { \
drivers/regulator/mp5416.c
54
.id = MP5416_BUCK ## _id, \
drivers/regulator/mp5416.c
65
.csel_mask = MP5416_MASK_BUCK ## _id ##_ILIM, \
drivers/regulator/mp5416.c
66
.vsel_reg = MP5416_REG_BUCK ## _id, \
drivers/regulator/mp5416.c
68
.enable_reg = MP5416_REG_BUCK ## _id, \
drivers/regulator/mp5416.c
80
#define MP5416LDO(_name, _id, _dval) \
drivers/regulator/mp5416.c
81
[MP5416_LDO ## _id] = { \
drivers/regulator/mp5416.c
82
.id = MP5416_LDO ## _id, \
drivers/regulator/mp5416.c
90
.vsel_reg = MP5416_REG_LDO ##_id, \
drivers/regulator/mp5416.c
92
.enable_reg = MP5416_REG_LDO ##_id, \
drivers/regulator/mpq7920.c
26
#define MPQ7920BUCK(_name, _id, _ilim) \
drivers/regulator/mpq7920.c
27
[MPQ7920_BUCK ## _id] = { \
drivers/regulator/mpq7920.c
28
.id = MPQ7920_BUCK ## _id, \
drivers/regulator/mpq7920.c
39
.csel_reg = MPQ7920_BUCK ##_id## _REG_C, \
drivers/regulator/mpq7920.c
43
MPQ7920_BUCK ## _id), \
drivers/regulator/mpq7920.c
44
.vsel_reg = MPQ7920_BUCK ##_id## _REG_A, \
drivers/regulator/mpq7920.c
47
.active_discharge_reg = MPQ7920_BUCK ##_id## _REG_B, \
drivers/regulator/mpq7920.c
49
.soft_start_reg = MPQ7920_BUCK ##_id## _REG_C, \
drivers/regulator/mpq7920.c
54
#define MPQ7920LDO(_name, _id, _ops, _ilim, _ilim_sz, _creg, _cmask) \
drivers/regulator/mpq7920.c
55
[MPQ7920_LDO ## _id] = { \
drivers/regulator/mpq7920.c
56
.id = MPQ7920_LDO ## _id, \
drivers/regulator/mpq7920.c
64
.vsel_reg = MPQ7920_LDO ##_id## _REG_A, \
drivers/regulator/mpq7920.c
70
.enable_reg = (_id == 1) ? 0 : MPQ7920_REG_REGULATOR_EN,\
drivers/regulator/mpq7920.c
72
MPQ7920_LDO ##_id + 1), \
drivers/regulator/mpq7920.c
75
.active_discharge_reg = MPQ7920_LDO ##_id## _REG_B, \
drivers/regulator/mt6311-regulator.c
48
#define MT6311_BUCK(_id) \
drivers/regulator/mt6311-regulator.c
50
.name = #_id,\
drivers/regulator/mt6311-regulator.c
52
.of_match = of_match_ptr(#_id),\
drivers/regulator/mt6311-regulator.c
55
.id = MT6311_ID_##_id,\
drivers/regulator/mt6311-regulator.c
66
#define MT6311_LDO(_id) \
drivers/regulator/mt6311-regulator.c
68
.name = #_id,\
drivers/regulator/mt6311-regulator.c
70
.of_match = of_match_ptr(#_id),\
drivers/regulator/mt6311-regulator.c
73
.id = MT6311_ID_##_id,\
drivers/regulator/palmas-regulator.c
319
#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
drivers/regulator/palmas-regulator.c
320
[PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
drivers/regulator/palmas-regulator.c
321
.id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
drivers/regulator/palmas-regulator.c
355
#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
drivers/regulator/palmas-regulator.c
356
[TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
drivers/regulator/palmas-regulator.c
357
.id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
drivers/regulator/pf8x00-regulator.c
381
#define PF8X00LDO(_id, _name, base, voltages) \
drivers/regulator/pf8x00-regulator.c
382
[PF8X00_LDO ## _id] = { \
drivers/regulator/pf8x00-regulator.c
390
.id = PF8X00_LDO ## _id, \
drivers/regulator/pf8x00-regulator.c
405
#define PF8X00BUCK(_id, _name, base, voltages) \
drivers/regulator/pf8x00-regulator.c
406
[PF8X00_BUCK ## _id] = { \
drivers/regulator/pf8x00-regulator.c
415
.id = PF8X00_BUCK ## _id, \
drivers/regulator/rc5t583-regulator.c
57
#define RC5T583_REG(_id, _en_reg, _en_bit, _disc_reg, _disc_bit, \
drivers/regulator/rc5t583-regulator.c
62
.deepsleep_reg = RC5T583_REG_##_id##DAC_DS, \
drivers/regulator/rc5t583-regulator.c
64
.deepsleep_id = RC5T583_DS_##_id, \
drivers/regulator/rc5t583-regulator.c
66
.name = "rc5t583-regulator-"#_id, \
drivers/regulator/rc5t583-regulator.c
67
.id = RC5T583_REGULATOR_##_id, \
drivers/regulator/rc5t583-regulator.c
72
.vsel_reg = RC5T583_REG_##_id##DAC, \
drivers/regulator/rk808-regulator.c
103
#define RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
111
.id = (_id), \
drivers/regulator/rk808-regulator.c
126
#define RK805_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
128
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
131
#define RK806_REGULATOR(_name, _supply_name, _id, _ops,\
drivers/regulator/rk808-regulator.c
134
[_id] = {\
drivers/regulator/rk808-regulator.c
139
.id = _id,\
drivers/regulator/rk808-regulator.c
159
#define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
161
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
164
#define RK801_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
166
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
169
#define RK816_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
171
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
174
#define RK817_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
176
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
drivers/regulator/rk808-regulator.c
179
#define RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
187
.id = (_id), \
drivers/regulator/rk808-regulator.c
196
#define RK801_DESC_SWITCH(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
198
RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
201
#define RK817_DESC_SWITCH(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
203
RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
206
#define RK8XX_DESC_SWITCH(_id, _match, _supply, _ereg, _emask) \
drivers/regulator/rk808-regulator.c
207
RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
drivers/regulator/rk808-regulator.c
79
#define RK817_BOOST_DESC(_id, _match, _supply, _min, _max, _step, _vreg,\
drivers/regulator/rk808-regulator.c
87
.id = (_id), \
drivers/regulator/rt5133-regulator.c
54
#define RT5133_LDO_REG_BASE(_id) (0x20 + ((_id) - 1) * 4)
drivers/regulator/rtq2134-regulator.c
26
#define RTQ2134_REG_FLT_RECORDBUCK(_id) (0x14 + (_id))
drivers/regulator/rtq2134-regulator.c
27
#define RTQ2134_REG_FLT_BUCKCTRL(_id) (0x37 + (_id))
drivers/regulator/rtq2134-regulator.c
270
#define RTQ2134_BUCK_DESC(_id) { \
drivers/regulator/rtq2134-regulator.c
272
.name = "rtq2134_buck" #_id, \
drivers/regulator/rtq2134-regulator.c
273
.of_match = of_match_ptr("buck" #_id), \
drivers/regulator/rtq2134-regulator.c
275
.id = RTQ2134_IDX_BUCK##_id, \
drivers/regulator/rtq2134-regulator.c
282
.vsel_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG1, \
drivers/regulator/rtq2134-regulator.c
284
.enable_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
drivers/regulator/rtq2134-regulator.c
286
.active_discharge_reg = RTQ2134_REG_BUCK##_id##_CFG0, \
drivers/regulator/rtq2134-regulator.c
289
.ramp_reg = RTQ2134_REG_BUCK##_id##_RSPCFG, \
drivers/regulator/rtq2134-regulator.c
296
.mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
drivers/regulator/rtq2134-regulator.c
298
.suspend_mode_reg = RTQ2134_REG_BUCK##_id##_DVS1CFG0, \
drivers/regulator/rtq2134-regulator.c
300
.suspend_enable_reg = RTQ2134_REG_BUCK##_id##_DVS1CFG0, \
drivers/regulator/rtq2134-regulator.c
302
.suspend_vsel_reg = RTQ2134_REG_BUCK##_id##_DVS1CFG1, \
drivers/regulator/rtq2134-regulator.c
304
.dvs_ctrl_reg = RTQ2134_REG_BUCK##_id##_DVSCFG, \
drivers/regulator/rtq2208-regulator.c
352
#define BUCK_INFO(_name, _id) \
drivers/regulator/rtq2208-regulator.c
355
.base = RTQ2208_REG_BUCK_##_id##_CFG0, \
drivers/regulator/rtq2208-regulator.c
356
.enable_reg = BUCK_RG_SHIFT(RTQ2208_REG_BUCK_##_id##_CFG0, 2), \
drivers/regulator/rtq2208-regulator.c
357
.dis_reg = RTQ2208_REG_BUCK_##_id##_CFG0, \
drivers/regulator/rtq2208-regulator.c
360
#define LDO_INFO(_name, _id) \
drivers/regulator/rtq2208-regulator.c
363
.base = RTQ2208_REG_LDO##_id##_CFG, \
drivers/regulator/rtq2208-regulator.c
364
.enable_reg = RTQ2208_REG_LDO##_id##_CFG, \
drivers/regulator/rtq2208-regulator.c
365
.dis_mask = RTQ2208_LDO##_id##_DISCHG_EN_MASK, \
drivers/regulator/rtq2208-regulator.c
366
.dis_on = RTQ2208_LDO##_id##_DISCHG_EN_MASK, \
drivers/regulator/rtq2208-regulator.c
367
.vsel_mask = RTQ2208_LDO##_id##_VOSEL_SD_MASK, \
drivers/regulator/s2dos05-regulator.c
35
#define BUCK_DESC(_name, _id, _ops, m, s, v, e, em, t, a) { \
drivers/regulator/s2dos05-regulator.c
37
.id = _id, \
drivers/regulator/s2dos05-regulator.c
58
#define LDO_DESC(_name, _id, _ops, m, s, v, e, em, t, a) { \
drivers/regulator/s2dos05-regulator.c
60
.id = _id, \
drivers/regulator/s2mps11.c
1049
#define regulator_desc_s2mpg11_buckx(_name, _id, _supply, _vrange, \
drivers/regulator/s2mps11.c
1051
regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, \
drivers/regulator/s2mps11.c
1056
s2mpg11_buck_to_ramp_mask(_id - S2MPG11_BUCK1), \
drivers/regulator/s2mps11.c
708
#define regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, _ops, \
drivers/regulator/s2mps11.c
717
.id = _id, \
drivers/regulator/s2mps11.c
809
#define regulator_desc_s2mpg1x_ldo_cmn(_name, _id, _supply, _ops, \
drivers/regulator/s2mps11.c
817
.id = _id, \
drivers/regulator/sc2731-regulator.c
130
#define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \
drivers/regulator/sc2731-regulator.c
132
.name = #_id, \
drivers/regulator/sc2731-regulator.c
133
.of_match = of_match_ptr(#_id), \
drivers/regulator/sc2731-regulator.c
136
.id = SC2731_##_id, \
drivers/regulator/slg51000-regulator.c
213
#define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
drivers/regulator/slg51000-regulator.c
214
[SLG51000_REGULATOR_##_id] = { \
drivers/regulator/slg51000-regulator.c
217
.id = SLG51000_REGULATOR_##_id, \
drivers/regulator/slg51000-regulator.c
227
.vsel_reg = SLG51000_##_id##_VSEL, \
drivers/regulator/slg51000-regulator.c
229
.enable_mask = BIT(SLG51000_REGULATOR_##_id), \
drivers/regulator/stm32-pwr.c
109
#define PWR_REG(_id, _name, _volt, _en, _supply) \
drivers/regulator/stm32-pwr.c
110
[_id] = { \
drivers/regulator/stm32-pwr.c
111
.id = _id, \
drivers/regulator/stpmic1_regulator.c
532
#define MATCH(_name, _id) \
drivers/regulator/stpmic1_regulator.c
533
[STPMIC1_##_id] = { \
drivers/regulator/stpmic1_regulator.c
535
.desc = &stpmic1_regulator_cfgs[STPMIC1_##_id].desc, \
drivers/regulator/tps65086-regulator.c
28
#define TPS65086_REGULATOR(_name, _of, _id, _nv, _vr, _vm, _er, _em, _lr, _dr, _dm) \
drivers/regulator/tps65086-regulator.c
29
[_id] = { \
drivers/regulator/tps65086-regulator.c
35
.id = _id, \
drivers/regulator/tps65086-regulator.c
52
#define TPS65086_SWITCH(_name, _of, _id, _er, _em) \
drivers/regulator/tps65086-regulator.c
53
[_id] = { \
drivers/regulator/tps65086-regulator.c
59
.id = _id, \
drivers/regulator/tps65090-regulator.c
185
#define tps65090_REG_DESC(_id, _sname, _en_reg, _en_bits, _nvolt, _volt, _ops) \
drivers/regulator/tps65090-regulator.c
187
.name = "TPS65090_RAILS"#_id, \
drivers/regulator/tps65090-regulator.c
189
.id = TPS65090_REGULATOR_##_id, \
drivers/regulator/tps65090-regulator.c
200
#define tps65090_REG_FIXEDV(_id, _sname, en_reg, _en_bits, _volt, _ops) \
drivers/regulator/tps65090-regulator.c
201
tps65090_REG_DESC(_id, _sname, en_reg, _en_bits, 1, _volt, _ops)
drivers/regulator/tps65090-regulator.c
203
#define tps65090_REG_SWITCH(_id, _sname, en_reg, _en_bits, _ops) \
drivers/regulator/tps65090-regulator.c
204
tps65090_REG_DESC(_id, _sname, en_reg, _en_bits, 0, 0, _ops)
drivers/regulator/tps65132-regulator.c
177
#define TPS65132_REGULATOR_DESC(_id, _name) \
drivers/regulator/tps65132-regulator.c
178
[TPS65132_REGULATOR_ID_##_id] = { \
drivers/regulator/tps65132-regulator.c
181
.id = TPS65132_REGULATOR_ID_##_id, \
drivers/regulator/tps65132-regulator.c
190
.vsel_reg = TPS65132_REG_##_id, \
drivers/regulator/tps65132-regulator.c
192
.active_discharge_on = TPS65132_REG_APPS_DIS_##_id, \
drivers/regulator/tps65132-regulator.c
193
.active_discharge_mask = TPS65132_REG_APPS_DIS_##_id, \
drivers/regulator/tps65217-regulator.c
22
#define TPS65217_REGULATOR(_name, _id, _of_match, _ops, _n, _vr, _vm, _em, \
drivers/regulator/tps65217-regulator.c
26
.id = _id, \
drivers/regulator/tps65218-regulator.c
23
#define TPS65218_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er, \
drivers/regulator/tps65218-regulator.c
29
.id = _id, \
drivers/regulator/tps65219-regulator.c
100
#define TPS65219_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er, \
drivers/regulator/tps65219-regulator.c
108
.id = _id, \
drivers/regulator/tps6586x-regulator.c
109
#define TPS6586X_REGULATOR(_id, _ops, _pin_name, vdata, vreg, shift, nbits, \
drivers/regulator/tps6586x-regulator.c
113
.name = "REG-" #_id, \
drivers/regulator/tps6586x-regulator.c
116
.id = TPS6586X_ID_##_id, \
drivers/regulator/tps6586x-regulator.c
132
#define TPS6586X_REGULATOR_LINEAR(_id, _ops, _pin_name, n_volt, min_uv, \
drivers/regulator/tps6586x-regulator.c
137
.name = "REG-" #_id, \
drivers/regulator/tps6586x-regulator.c
140
.id = TPS6586X_ID_##_id, \
drivers/regulator/tps6586x-regulator.c
157
#define TPS6586X_LDO(_id, _pname, vdata, vreg, shift, nbits, \
drivers/regulator/tps6586x-regulator.c
160
TPS6586X_REGULATOR(_id, rw, _pname, vdata, vreg, shift, nbits, \
drivers/regulator/tps6586x-regulator.c
164
#define TPS6586X_LDO_LINEAR(_id, _pname, n_volt, min_uv, uv_step, vreg, \
drivers/regulator/tps6586x-regulator.c
167
TPS6586X_REGULATOR_LINEAR(_id, rw_linear, _pname, n_volt, \
drivers/regulator/tps6586x-regulator.c
172
#define TPS6586X_FIXED_LDO(_id, _pname, vdata, vreg, shift, nbits, \
drivers/regulator/tps6586x-regulator.c
175
TPS6586X_REGULATOR(_id, ro, _pname, vdata, vreg, shift, nbits, \
drivers/regulator/tps6586x-regulator.c
179
#define TPS6586X_DVM(_id, _pname, n_volt, min_uv, uv_step, vreg, shift, \
drivers/regulator/tps6586x-regulator.c
182
TPS6586X_REGULATOR_LINEAR(_id, rw_linear, _pname, n_volt, \
drivers/regulator/tps65912-regulator.c
22
#define TPS65912_REGULATOR(_name, _id, _of_match, _ops, _vr, _er, _lr) \
drivers/regulator/tps65912-regulator.c
23
[_id] = { \
drivers/regulator/tps65912-regulator.c
27
.id = _id, \
drivers/regulator/tps6594-regulator.c
88
#define TPS6594_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er, \
drivers/regulator/tps6594-regulator.c
96
.id = _id, \
drivers/regulator/tps68470-regulator.c
32
#define TPS68470_REGULATOR(_name, _id, _ops, _n, \
drivers/regulator/tps68470-regulator.c
36
.id = _id, \
drivers/reset/reset-uniphier.c
27
#define UNIPHIER_RESET(_id, _reg, _bit) \
drivers/reset/reset-uniphier.c
29
.id = (_id), \
drivers/reset/reset-uniphier.c
34
#define UNIPHIER_RESETX(_id, _reg, _bit) \
drivers/reset/reset-uniphier.c
36
.id = (_id), \
drivers/s390/net/qeth_l3_sys.c
16
#define QETH_DEVICE_ATTR(_id, _name, _mode, _show, _store) \
drivers/s390/net/qeth_l3_sys.c
17
struct device_attribute dev_attr_##_id = __ATTR(_name, _mode, _show, _store)
drivers/soc/tegra/pmc.c
320
#define TEGRA_WAKE_SIMPLE(_name, _id) \
drivers/soc/tegra/pmc.c
323
.id = _id, \
drivers/soc/tegra/pmc.c
331
#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
drivers/soc/tegra/pmc.c
334
.id = _id, \
drivers/soc/tegra/pmc.c
342
#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
drivers/soc/tegra/pmc.c
345
.id = _id, \
drivers/soc/tegra/pmc.c
3700
#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \
drivers/soc/tegra/pmc.c
3702
.id = (_id), \
drivers/soc/tegra/pmc.c
3710
#define TEGRA_IO_PIN_DESC(_id, _name) \
drivers/soc/tegra/pmc.c
3712
.number = (_id), \
drivers/staging/media/deprecated/atmel/atmel-isc-base.c
1629
#define ISC_CTRL_OFF(_name, _id, _name_str) \
drivers/staging/media/deprecated/atmel/atmel-isc-base.c
1632
.id = _id, \
drivers/staging/media/deprecated/atmel/atmel-isc-base.c
1647
#define ISC_CTRL_GAIN(_name, _id, _name_str) \
drivers/staging/media/deprecated/atmel/atmel-isc-base.c
1650
.id = _id, \
drivers/usb/phy/phy-ulpi.c
27
#define ULPI_INFO(_id, _name) \
drivers/usb/phy/phy-ulpi.c
29
.id = (_id), \
drivers/vfio/pci/xe/main.c
552
#define INTEL_PCI_VFIO_DEVICE(_id) { \
drivers/vfio/pci/xe/main.c
553
PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_INTEL, (_id)) \
fs/erofs/sysfs.c
31
#define EROFS_ATTR(_name, _mode, _id) \
fs/erofs/sysfs.c
34
.attr_id = attr_##_id, \
fs/erofs/sysfs.c
39
#define EROFS_ATTR_OFFSET(_name, _mode, _id, _struct) \
fs/erofs/sysfs.c
42
.attr_id = attr_##_id, \
fs/erofs/sysfs.c
47
#define EROFS_ATTR_RW(_name, _id, _struct) \
fs/erofs/sysfs.c
48
EROFS_ATTR_OFFSET(_name, 0644, _id, _struct)
fs/erofs/sysfs.c
50
#define EROFS_RO_ATTR(_name, _id, _struct) \
fs/erofs/sysfs.c
51
EROFS_ATTR_OFFSET(_name, 0444, _id, _struct)
fs/ext4/sysfs.c
172
#define EXT4_ATTR(_name,_mode,_id) \
fs/ext4/sysfs.c
175
.attr_id = attr_##_id, \
fs/ext4/sysfs.c
182
#define EXT4_ATTR_OFFSET(_name,_mode,_id,_struct,_elname) \
fs/ext4/sysfs.c
185
.attr_id = attr_##_id, \
fs/ext4/sysfs.c
227
#define EXT4_ATTR_PTR(_name,_mode,_id,_ptr) \
fs/ext4/sysfs.c
230
.attr_id = attr_##_id, \
fs/ubifs/sysfs.c
25
#define UBIFS_ATTR(_name, _mode, _id) \
fs/ubifs/sysfs.c
28
.attr_id = attr_##_id, \
include/drm/intel/pciids.h
29
#define INTEL_PCI_DEVICE(_id, _info) { \
include/drm/intel/pciids.h
30
PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
include/drm/intel/pciids.h
34
#define INTEL_VGA_DEVICE(_id, _info) { \
include/drm/intel/pciids.h
35
PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
include/linux/bpf.h
2565
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \
include/linux/bpf.h
2568
#define BPF_MAP_TYPE(_id, _ops) \
include/linux/bpf.h
2570
#define BPF_LINK_TYPE(_id, _name)
include/linux/clk/at91_pmc.h
146
#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
include/linux/ieee80211.h
2718
#define for_each_element_id(element, _id, data, datalen) \
include/linux/ieee80211.h
2720
if (element->id == (_id))
include/linux/mfd/core.h
17
#define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \
include/linux/mfd/core.h
28
.id = (_id), \
include/linux/mfd/core.h
31
#define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \
include/linux/mfd/core.h
32
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, true, NULL)
include/linux/mfd/core.h
34
#define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \
include/linux/mfd/core.h
35
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, 0, false, NULL)
include/linux/mfd/core.h
37
#define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \
include/linux/mfd/core.h
38
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, _match)
include/linux/mfd/core.h
40
#define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \
include/linux/mfd/core.h
41
MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, false, NULL)
include/linux/mod_devicetable.h
441
#define BCMA_CORE(_manuf, _id, _rev, _class) \
include/linux/mod_devicetable.h
442
{ .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
include/linux/mod_devicetable.h
615
#define MDIO_ID_ARGS(_id) \
include/linux/mod_devicetable.h
616
((_id)>>31) & 1, ((_id)>>30) & 1, ((_id)>>29) & 1, ((_id)>>28) & 1, \
include/linux/mod_devicetable.h
617
((_id)>>27) & 1, ((_id)>>26) & 1, ((_id)>>25) & 1, ((_id)>>24) & 1, \
include/linux/mod_devicetable.h
618
((_id)>>23) & 1, ((_id)>>22) & 1, ((_id)>>21) & 1, ((_id)>>20) & 1, \
include/linux/mod_devicetable.h
619
((_id)>>19) & 1, ((_id)>>18) & 1, ((_id)>>17) & 1, ((_id)>>16) & 1, \
include/linux/mod_devicetable.h
620
((_id)>>15) & 1, ((_id)>>14) & 1, ((_id)>>13) & 1, ((_id)>>12) & 1, \
include/linux/mod_devicetable.h
621
((_id)>>11) & 1, ((_id)>>10) & 1, ((_id)>>9) & 1, ((_id)>>8) & 1, \
include/linux/mod_devicetable.h
622
((_id)>>7) & 1, ((_id)>>6) & 1, ((_id)>>5) & 1, ((_id)>>4) & 1, \
include/linux/mod_devicetable.h
623
((_id)>>3) & 1, ((_id)>>2) & 1, ((_id)>>1) & 1, (_id) & 1
include/linux/nd.h
27
#define NVDIMM_EVENT_VAR(_id) event_attr_##_id
include/linux/nd.h
28
#define NVDIMM_EVENT_PTR(_id) (&event_attr_##_id.attr.attr)
include/linux/nd.h
30
#define NVDIMM_EVENT_ATTR(_name, _id) \
include/linux/nd.h
31
PMU_EVENT_ATTR(_name, NVDIMM_EVENT_VAR(_id), _id, \
include/linux/perf_event.h
2064
#define PMU_EVENT_ATTR(_name, _var, _id, _show) \
include/linux/perf_event.h
2067
.id = _id, \
include/linux/perf_event.h
2077
#define PMU_EVENT_ATTR_ID(_name, _show, _id) \
include/linux/perf_event.h
2080
.id = _id, } \
include/linux/regmap.h
1599
#define REGMAP_IRQ_REG_LINE(_id, _reg_bits) \
include/linux/regmap.h
1600
[_id] = { \
include/linux/regmap.h
1601
.mask = BIT((_id) % (_reg_bits)), \
include/linux/regmap.h
1602
.reg_offset = (_id) / (_reg_bits), \
include/linux/sh_clk.h
200
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
include/linux/sh_clk.h
201
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
include/linux/soc/mediatek/mtk_wed.h
293
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
include/linux/soc/mediatek/mtk_wed.h
294
(_dev)->ops->msg_update(_dev, _id, _msg, _len)
include/linux/soc/mediatek/mtk_wed.h
323
#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV
include/linux/soc/pxa/cpu.h
102
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
103
_id == 0x688; \
include/linux/soc/pxa/cpu.h
112
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
113
_id == 0x689; \
include/linux/soc/pxa/cpu.h
122
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
123
_id == 0x603 || _id == 0x682; \
include/linux/soc/pxa/cpu.h
132
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
133
_id == 0x683; \
include/linux/soc/pxa/cpu.h
142
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
143
_id == 0x693; \
include/linux/soc/pxa/cpu.h
208
unsigned int _id = (id) >> 13 & 0x7; \
include/linux/soc/pxa/cpu.h
209
_id <= 0x2; \
include/linux/soc/pxa/cpu.h
61
unsigned int _id = (id) & 0xf3f0; \
include/linux/soc/pxa/cpu.h
62
_id == 0x2120; \
include/linux/soc/pxa/cpu.h
67
unsigned int _id = (id) & 0xf3ff; \
include/linux/soc/pxa/cpu.h
68
_id <= 0x2105; \
include/linux/soc/pxa/cpu.h
73
unsigned int _id = (id) & 0xffff; \
include/linux/soc/pxa/cpu.h
74
_id == 0x2d06; \
include/linux/soc/pxa/cpu.h
79
unsigned int _id = (id) & 0xf300; \
include/linux/soc/pxa/cpu.h
80
_id == 0x2100; \
include/linux/soc/pxa/cpu.h
92
unsigned int _id = (id) >> 4 & 0xfff; \
include/linux/soc/pxa/cpu.h
93
_id == 0x411; \
include/net/devlink.h
1298
#define DEVLINK_TRAP_GENERIC(_type, _init_action, _id, _group_id, \
include/net/devlink.h
1304
.id = DEVLINK_TRAP_GENERIC_ID_##_id, \
include/net/devlink.h
1305
.name = DEVLINK_TRAP_GENERIC_NAME_##_id, \
include/net/devlink.h
1310
#define DEVLINK_TRAP_DRIVER(_type, _init_action, _id, _name, _group_id, \
include/net/devlink.h
1316
.id = _id, \
include/net/devlink.h
1322
#define DEVLINK_TRAP_GROUP_GENERIC(_id, _policer_id) \
include/net/devlink.h
1324
.name = DEVLINK_TRAP_GROUP_GENERIC_NAME_##_id, \
include/net/devlink.h
1325
.id = DEVLINK_TRAP_GROUP_GENERIC_ID_##_id, \
include/net/devlink.h
1330
#define DEVLINK_TRAP_POLICER(_id, _rate, _burst, _max_rate, _min_rate, \
include/net/devlink.h
1333
.id = _id, \
include/net/devlink.h
621
#define DEVLINK_PARAM_GENERIC(_id, _cmodes, _get, _set, _validate) \
include/net/devlink.h
623
.id = DEVLINK_PARAM_GENERIC_ID_##_id, \
include/net/devlink.h
624
.name = DEVLINK_PARAM_GENERIC_##_id##_NAME, \
include/net/devlink.h
625
.type = DEVLINK_PARAM_GENERIC_##_id##_TYPE, \
include/net/devlink.h
633
#define DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes, _get, _set, _validate) \
include/net/devlink.h
635
.id = _id, \
include/net/devlink.h
644
#define DEVLINK_PARAM_GENERIC_WITH_DEFAULTS(_id, _cmodes, _get, _set, \
include/net/devlink.h
648
.id = DEVLINK_PARAM_GENERIC_ID_##_id, \
include/net/devlink.h
649
.name = DEVLINK_PARAM_GENERIC_##_id##_NAME, \
include/net/devlink.h
650
.type = DEVLINK_PARAM_GENERIC_##_id##_TYPE, \
include/net/devlink.h
660
#define DEVLINK_PARAM_DRIVER_WITH_DEFAULTS(_id, _name, _type, _cmodes, \
include/net/devlink.h
664
.id = _id, \
include/net/dsa.h
1246
#define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes) \
include/net/dsa.h
1247
DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes, \
include/net/dsa.h
175
#define dsa_lags_foreach_id(_id, _dst) \
include/net/dsa.h
176
for ((_id) = 1; (_id) <= (_dst)->lags_len; (_id)++) \
include/net/dsa.h
177
if ((_dst)->lags[(_id) - 1])
include/rdma/uverbs_std_types.h
19
#define _uobj_check_id(_id) ((_id) * typecheck(u32, _id))
include/rdma/uverbs_std_types.h
24
#define uobj_get_read(_type, _id, _attrs) \
include/rdma/uverbs_std_types.h
26
_uobj_check_id(_id), UVERBS_LOOKUP_READ, \
include/rdma/uverbs_std_types.h
40
#define uobj_get_obj_read(_object, _type, _id, _attrs) \
include/rdma/uverbs_std_types.h
42
uobj_get_read(_type, _id, _attrs)))
include/rdma/uverbs_std_types.h
44
#define uobj_get_write(_type, _id, _attrs) \
include/rdma/uverbs_std_types.h
46
_uobj_check_id(_id), UVERBS_LOOKUP_WRITE, \
include/rdma/uverbs_std_types.h
51
#define uobj_perform_destroy(_type, _id, _attrs) \
include/rdma/uverbs_std_types.h
53
_uobj_check_id(_id), _attrs)
include/rdma/uverbs_std_types.h
58
#define uobj_get_destroy(_type, _id, _attrs) \
include/rdma/uverbs_std_types.h
59
__uobj_get_destroy(uobj_get_type(_attrs, _type), _uobj_check_id(_id), \
include/soc/bcm2835/raspberrypi-firmware.h
172
#define RPI_FIRMWARE_CLK_RATE_REQUEST(_id) \
include/soc/bcm2835/raspberrypi-firmware.h
174
.id = cpu_to_le32(_id), \
kernel/bpf/btf.c
5992
#define BPF_MAP_TYPE(_id, _ops)
kernel/bpf/btf.c
5993
#define BPF_LINK_TYPE(_id, _name)
kernel/bpf/btf.c
5996
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \
kernel/bpf/btf.c
5997
prog_ctx_type _id##_prog; \
kernel/bpf/btf.c
5998
kern_ctx_type _id##_kern;
kernel/bpf/btf.c
6013
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \
kernel/bpf/btf.c
6014
[_id] = __ctx_convert##_id,
kernel/bpf/syscall.c
2269
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \
kernel/bpf/syscall.c
2270
[_id] = & _name ## _prog_ops,
kernel/bpf/syscall.c
2271
#define BPF_MAP_TYPE(_id, _ops)
kernel/bpf/syscall.c
2272
#define BPF_LINK_TYPE(_id, _name)
kernel/bpf/syscall.c
3356
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type)
kernel/bpf/syscall.c
3357
#define BPF_MAP_TYPE(_id, _ops)
kernel/bpf/syscall.c
3358
#define BPF_LINK_TYPE(_id, _name) [_id] = #_name,
kernel/bpf/syscall.c
72
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type)
kernel/bpf/syscall.c
73
#define BPF_MAP_TYPE(_id, _ops) \
kernel/bpf/syscall.c
74
[_id] = &_ops,
kernel/bpf/syscall.c
75
#define BPF_LINK_TYPE(_id, _name)
kernel/bpf/verifier.c
37
#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \
kernel/bpf/verifier.c
38
[_id] = & _name ## _verifier_ops,
kernel/bpf/verifier.c
39
#define BPF_MAP_TYPE(_id, _ops)
kernel/bpf/verifier.c
40
#define BPF_LINK_TYPE(_id, _name)
kernel/time/posix-timers.c
76
#define scoped_timer_get_or_fail(_id) \
kernel/time/posix-timers.c
77
scoped_cond_guard(lock_timer, return -EINVAL, _id)
net/6lowpan/nhc.h
25
_hdrlen, _id, _idmask, \
net/6lowpan/nhc.h
31
.id = _id, \
net/devlink/trap.c
1048
#define DEVLINK_TRAP_GROUP(_id) \
net/devlink/trap.c
1050
.id = DEVLINK_TRAP_GROUP_GENERIC_ID_##_id, \
net/devlink/trap.c
1051
.name = DEVLINK_TRAP_GROUP_GENERIC_NAME_##_id, \
net/devlink/trap.c
944
#define DEVLINK_TRAP(_id, _type) \
net/devlink/trap.c
947
.id = DEVLINK_TRAP_GENERIC_ID_##_id, \
net/devlink/trap.c
948
.name = DEVLINK_TRAP_GENERIC_NAME_##_id, \
sound/core/control.c
1346
struct snd_ctl_elem_id __user *_id)
sound/core/control.c
1353
if (copy_from_user(&id, _id, sizeof(id)))
sound/core/control.c
1367
struct snd_ctl_elem_id __user *_id)
sound/core/control.c
1374
if (copy_from_user(&id, _id, sizeof(id)))
sound/core/control.c
1763
struct snd_ctl_elem_id __user *_id)
sound/core/control.c
1767
if (copy_from_user(&id, _id, sizeof(id)))
sound/pci/emu10k1/emufx.c
660
struct emu10k1_ctl_elem_id *_id)
sound/pci/emu10k1/emufx.c
662
struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
sound/pci/emu10k1/emufx.c
751
struct emu10k1_ctl_elem_id __user *_id =
sound/pci/emu10k1/emufx.c
756
else if (copy_from_user(ret, _id, sizeof(*ret)))
sound/soc/codecs/idt821034.c
397
#define IDT821034_ID_GET_CHAN(_id) ((_id) & 0x03)
sound/soc/codecs/idt821034.c
398
#define IDT821034_ID_GET_DIR(_id) ((_id) & (1 << 3))
sound/soc/codecs/idt821034.c
399
#define IDT821034_ID_IS_OUT(_id) (IDT821034_ID_GET_DIR(_id) == IDT821034_DIR_OUT)
sound/soc/intel/avs/board_selection.c
362
#define AVS_MACH_ENTRY(_id, _mach) \
sound/soc/intel/avs/board_selection.c
363
{ .id = PCI_DEVICE_ID_INTEL_##_id, .machs = (_mach), }
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
429
#define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg) \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
430
[MT8183_MEMIF_##_id] = { \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
431
.name = #_id, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
432
.id = MT8183_MEMIF_##_id, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
433
.reg_ofs_base = AFE_##_id##_BASE, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
434
.reg_ofs_cur = AFE_##_id##_CUR, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
435
.reg_ofs_end = AFE_##_id##_END, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
436
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
437
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
438
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
440
.fs_shift = _id##_MODE_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
441
.fs_maskbit = _id##_MODE_MASK, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
443
.mono_shift = _id##_DATA_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
445
.enable_shift = _id##_ON_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
448
.hd_shift = _id##_HD_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
449
.hd_align_mshift = _id##_HD_ALIGN_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
456
#define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
457
MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
495
#define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit) \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
496
[MT8183_IRQ_##_id] = { \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
497
.id = MT8183_IRQ_##_id, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
498
.irq_cnt_reg = AFE_IRQ_MCU_CNT##_id, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
505
.irq_en_shift = IRQ##_id##_MCU_ON_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
507
.irq_clr_shift = IRQ##_id##_MCU_CLR_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
510
#define MT8183_AFE_IRQ(_id) \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
511
MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
512
IRQ##_id##_MCU_MODE_SFT, \
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
513
IRQ##_id##_MCU_MODE_MASK)
sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
515
#define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
27
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
28
.id = _id, \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
37
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
38
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
41
#define GATE_AUD0(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
42
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
44
#define GATE_AUD1(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
45
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
47
#define GATE_AUD2(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
48
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
28
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
29
.id = _id, \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
38
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
39
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
42
#define GATE_AUD0(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
43
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
45
#define GATE_AUD1(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
46
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
48
#define GATE_AUD3(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
49
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
51
#define GATE_AUD4(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
52
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
54
#define GATE_AUD5(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
55
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
57
#define GATE_AUD6(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
58
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1621
#define MT8189_DL_MEMIF(_id) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1622
[MT8189_MEMIF_##_id] = { \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1623
.name = #_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1624
.id = MT8189_MEMIF_##_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1625
.reg_ofs_base = AFE_##_id##_BASE, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1626
.reg_ofs_cur = AFE_##_id##_CUR, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1627
.reg_ofs_end = AFE_##_id##_END, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1628
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1629
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1630
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1631
.fs_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1632
.fs_shift = _id##_SEL_FS_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1633
.fs_maskbit = _id##_SEL_FS_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1634
.mono_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1635
.mono_shift = _id##_MONO_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1636
.enable_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1637
.enable_shift = _id##_ON_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1638
.hd_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1639
.hd_shift = _id##_HD_MODE_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1640
.hd_align_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1641
.hd_align_mshift = _id##_HALIGN_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1646
.pbuf_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1647
.pbuf_mask = _id##_PBUF_SIZE_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1648
.pbuf_shift = _id##_PBUF_SIZE_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1649
.minlen_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1650
.minlen_mask = _id##_MINLEN_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1651
.minlen_shift = _id##_MINLEN_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1654
#define MT8189_MULTI_DL_MEMIF(_id) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1655
[MT8189_MEMIF_##_id] = { \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1656
.name = #_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1657
.id = MT8189_MEMIF_##_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1658
.reg_ofs_base = AFE_##_id##_BASE, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1659
.reg_ofs_cur = AFE_##_id##_CUR, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1660
.reg_ofs_end = AFE_##_id##_END, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1661
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1662
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1663
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1664
.fs_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1665
.fs_shift = _id##_SEL_FS_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1666
.fs_maskbit = _id##_SEL_FS_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1669
.enable_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1670
.enable_shift = _id##_ON_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1671
.hd_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1672
.hd_shift = _id##_HD_MODE_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1673
.hd_align_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1674
.hd_align_mshift = _id##_HALIGN_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1679
.pbuf_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1680
.pbuf_mask = _id##_PBUF_SIZE_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1681
.pbuf_shift = _id##_PBUF_SIZE_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1682
.minlen_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1683
.minlen_mask = _id##_MINLEN_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1684
.minlen_shift = _id##_MINLEN_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1685
.ch_num_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1686
.ch_num_maskbit = _id##_NUM_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1687
.ch_num_shift = _id##_NUM_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1690
#define MT8189_UL_MEMIF(_id, _fs_shift, _fs_maskbit, _mono_shift) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1691
[MT8189_MEMIF_##_id] = { \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1692
.name = #_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1693
.id = MT8189_MEMIF_##_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1694
.reg_ofs_base = AFE_##_id##_BASE, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1695
.reg_ofs_cur = AFE_##_id##_CUR, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1696
.reg_ofs_end = AFE_##_id##_END, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1697
.reg_ofs_base_msb = AFE_##_id##_BASE_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1698
.reg_ofs_cur_msb = AFE_##_id##_CUR_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1699
.reg_ofs_end_msb = AFE_##_id##_END_MSB, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1700
.fs_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1703
.mono_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1705
.enable_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1706
.enable_shift = _id##_ON_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1707
.hd_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1708
.hd_shift = _id##_HD_MODE_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1709
.hd_align_reg = AFE_##_id##_CON0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1710
.hd_align_mshift = _id##_HALIGN_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1773
#define MT8189_AFE_IRQ(_id) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1774
[MT8189_IRQ_##_id] = { \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1775
.id = MT8189_IRQ_##_id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1776
.irq_cnt_reg = AFE_IRQ##_id##_MCU_CFG1, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1779
.irq_fs_reg = AFE_IRQ##_id##_MCU_CFG0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1780
.irq_fs_shift = AFE_IRQ##_id##_MCU_FS_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1781
.irq_fs_maskbit = AFE_IRQ##_id##_MCU_FS_MASK, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1782
.irq_en_reg = AFE_IRQ##_id##_MCU_CFG0, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1783
.irq_en_shift = AFE_IRQ##_id##_MCU_ON_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1784
.irq_clr_reg = AFE_IRQ##_id##_MCU_CFG1, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1785
.irq_clr_shift = AFE_IRQ##_id##_CLR_CFG_SFT, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1788
#define MT8189_AFE_TDM_IRQ(_id) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
1789
[MT8189_IRQ_##_id] = { \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
394
#define MT8189_FE_DAI_PLAYBACK(_name, _id, max_ch) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
397
.id = _id, \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
408
#define MT8189_FE_DAI_CAPTURE(_name, _id, max_ch) \
sound/soc/mediatek/mt8189/mt8189-afe-pcm.c
411
.id = _id, \
sound/soc/mediatek/mt8189/mt8189-dai-i2s.c
1329
#define MT8189_I2S_DAI(_name, _id, max_ch, dir) \
sound/soc/mediatek/mt8189/mt8189-dai-i2s.c
1332
.id = _id, \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
28
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
29
.id = _id, \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
38
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
39
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
42
#define GATE_AUD0(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
43
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
45
#define GATE_AUD1(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
46
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
48
#define GATE_AUD3(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
49
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
51
#define GATE_AUD4(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
52
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
54
#define GATE_AUD5(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
55
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
57
#define GATE_AUD6(_id, _name, _parent, _bit) \
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
58
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
