__mdiobus_write
ret = __mdiobus_write(bus, switch_phy_id, reg, lower_16_bits(val));
ret = __mdiobus_write(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS),
ret = __mdiobus_write(bus, switch_phy_id, reg, page);
res = __mdiobus_write(bus, sw_addr, reg - smdio_badr, val);
res = __mdiobus_write(bus, sw_addr, GSW1XX_SMDIO_BADR, smdio_badr);
ret = __mdiobus_write(mdev->bus, ((tmp & 0xE0) >> 5),
return __mdiobus_write(sbus, p, r, val);
res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16));
res = __mdiobus_write(bus, addr, reg_addr, (u16)reg);
res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16));
res = __mdiobus_write(bus, addr, reg_addr, (u16)reg);
res = __mdiobus_write(bus, addr, reg_data, (u16)(val >> 16));
res = __mdiobus_write(bus, addr, reg_data, (u16)val);
err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_EXT_PAGE_ACCESS,
ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_ADDR_HIGH,
ret = __mdiobus_write(mdiodev->bus, mdiodev->addr,
return __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_DATA_HIGH,
EXPORT_SYMBOL(__mdiobus_write);
ret = __mdiobus_write(bus, addr, regnum, new);
err = __mdiobus_write(bus, addr, regnum, val);
err = __mdiobus_write(bus, addr, regnum, val);
return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum,
__mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
__mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
__mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
return __mdiobus_write(mdiodev->bus, mdiodev->addr, regnum, val);
return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,