arch/alpha/boot/stdio.c

18

unsigned int __base = (base); \

arch/alpha/boot/stdio.c

20

__rem = ((unsigned long long)(n)) % __base; \

arch/alpha/boot/stdio.c

21

(n) = ((unsigned long long)(n)) / __base; \

arch/arm/include/asm/div64.h

26

register unsigned int __base asm("r4") = base;

arch/arm/include/asm/div64.h

35

: "r" (__base)

arch/m68k/include/asm/div64.h

19

unsigned long __base = (base); \

arch/m68k/include/asm/div64.h

25

: "d" (__base), "0" (__n.n32[0])); \

arch/m68k/include/asm/div64.h

29

: "d" (__base), "1" (__upper), "0" (__n.n32[1])); \

arch/powerpc/boot/stdio.c

33

unsigned int __base = (base); \

arch/powerpc/boot/stdio.c

35

__rem = ((unsigned long long)(n)) % __base; \

arch/powerpc/boot/stdio.c

36

(n) = ((unsigned long long)(n)) / __base; \

arch/powerpc/boot/stdio.c

49

unsigned int __base = (base); \

arch/powerpc/boot/stdio.c

53

__rem = (unsigned int)(n) % __base; \

arch/powerpc/boot/stdio.c

54

(n) = (unsigned int)(n) / __base; \

arch/powerpc/boot/stdio.c

56

__rem = __div64_32(&(n), __base); \

arch/x86/include/asm/div64.h

24

unsigned long __upper, __low, __high, __mod, __base; \

arch/x86/include/asm/div64.h

25

__base = (base); \

arch/x86/include/asm/div64.h

26

if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \

arch/x86/include/asm/div64.h

27

__mod = n & (__base - 1); \

arch/x86/include/asm/div64.h

28

n >>= ilog2(__base); \

arch/x86/include/asm/div64.h

33

__upper = __high % (__base); \

arch/x86/include/asm/div64.h

34

__high = __high / (__base); \

arch/x86/include/asm/div64.h

37

: "rm" (__base), "0" (__low), "1" (__upper)); \

drivers/clocksource/timer-nxp-pit.c

21

#define PITMCR(__base) (__base)

drivers/clocksource/timer-nxp-pit.c

26

#define PITLDVAL(__base) (__base)

drivers/clocksource/timer-nxp-pit.c

27

#define PITTCTRL(__base) ((__base) + 0x08)

drivers/clocksource/timer-nxp-pit.c

30

#define PITCVAL(__base) ((__base) + 0x04)

drivers/clocksource/timer-nxp-pit.c

35

#define PITTFLG(__base) ((__base) + 0x0c)

drivers/clocksource/timer-nxp-stm.c

25

#define STM_CR(__base) (__base)

drivers/clocksource/timer-nxp-stm.c

32

#define STM_CNT(__base) ((__base) + 0x04)

drivers/clocksource/timer-nxp-stm.c

34

#define STM_CCR0(__base) ((__base) + 0x10)

drivers/clocksource/timer-nxp-stm.c

35

#define STM_CCR1(__base) ((__base) + 0x20)

drivers/clocksource/timer-nxp-stm.c

36

#define STM_CCR2(__base) ((__base) + 0x30)

drivers/clocksource/timer-nxp-stm.c

37

#define STM_CCR3(__base) ((__base) + 0x40)

drivers/clocksource/timer-nxp-stm.c

41

#define STM_CIR0(__base) ((__base) + 0x14)

drivers/clocksource/timer-nxp-stm.c

42

#define STM_CIR1(__base) ((__base) + 0x24)

drivers/clocksource/timer-nxp-stm.c

43

#define STM_CIR2(__base) ((__base) + 0x34)

drivers/clocksource/timer-nxp-stm.c

44

#define STM_CIR3(__base) ((__base) + 0x44)

drivers/clocksource/timer-nxp-stm.c

48

#define STM_CMP0(__base) ((__base) + 0x18)

drivers/clocksource/timer-nxp-stm.c

49

#define STM_CMP1(__base) ((__base) + 0x28)

drivers/clocksource/timer-nxp-stm.c

50

#define STM_CMP2(__base) ((__base) + 0x38)

drivers/clocksource/timer-nxp-stm.c

51

#define STM_CMP3(__base) ((__base) + 0x48)

drivers/gpu/drm/vmwgfx/ttm_object.h

285

#define ttm_base_object_kfree(__object, __base)\

drivers/gpu/drm/vmwgfx/ttm_object.h

286

kfree_rcu(__object, __base.rhead)

drivers/iio/adc/nxp-sar-adc.c

100

#define NXP_SAR_ADC_NCMR0(__base) ((__base) + 0xa4)

drivers/iio/adc/nxp-sar-adc.c

101

#define NXP_SAR_ADC_NCMR1(__base) ((__base) + 0xa8)

drivers/iio/adc/nxp-sar-adc.c

39

#define NXP_SAR_ADC_CDR(__base, __channel) (((__base) + 0x100) + ((__channel) * 0x4))

drivers/iio/adc/nxp-sar-adc.c

45

#define NXP_SAR_ADC_MCR(__base) ((__base) + 0x00)

drivers/iio/adc/nxp-sar-adc.c

59

#define NXP_SAR_ADC_MSR(__base) ((__base) + 0x04)

drivers/iio/adc/nxp-sar-adc.c

65

#define NXP_SAR_ADC_ISR(__base) ((__base) + 0x10)

drivers/iio/adc/nxp-sar-adc.c

70

#define NXP_SAR_ADC_CEOCFR0(__base) ((__base) + 0x14)

drivers/iio/adc/nxp-sar-adc.c

71

#define NXP_SAR_ADC_CEOCFR1(__base) ((__base) + 0x18)

drivers/iio/adc/nxp-sar-adc.c

76

#define NXP_SAR_ADC_IMR(__base) ((__base) + 0x20)

drivers/iio/adc/nxp-sar-adc.c

79

#define NXP_SAR_ADC_CIMR0(__base) ((__base) + 0x24)

drivers/iio/adc/nxp-sar-adc.c

80

#define NXP_SAR_ADC_CIMR1(__base) ((__base) + 0x28)

drivers/iio/adc/nxp-sar-adc.c

83

#define NXP_SAR_ADC_DMAE(__base) ((__base) + 0x40)

drivers/iio/adc/nxp-sar-adc.c

89

#define NXP_SAR_ADC_DMAR0(__base) ((__base) + 0x44)

drivers/iio/adc/nxp-sar-adc.c

90

#define NXP_SAR_ADC_DMAR1(__base) ((__base) + 0x48)

drivers/iio/adc/nxp-sar-adc.c

93

#define NXP_SAR_ADC_CTR0(__base) ((__base) + 0x94)

drivers/iio/adc/nxp-sar-adc.c

94

#define NXP_SAR_ADC_CTR1(__base) ((__base) + 0x98)

drivers/net/ethernet/amd/sunlance.c

277

do { void __iomem *__base = (__lp)->lregs; \

drivers/net/ethernet/amd/sunlance.c

278

sbus_writew(LE_CSR0, __base + RAP); \

drivers/net/ethernet/amd/sunlance.c

279

sbus_writew(LE_C0_STOP, __base + RDP); \

drivers/net/ethernet/qlogic/qed/qed.h

945

#define GET_GTT_REG_ADDR(__base, __offset, __idx) \

drivers/net/ethernet/qlogic/qed/qed.h

946

((__base) + __offset ## _GTT_OFFSET((__idx)))

drivers/net/ethernet/qlogic/qed/qed.h

948

#define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \

drivers/net/ethernet/qlogic/qed/qed.h

949

((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx)))

drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

20

static const struct __base mt7996_reg_base[] = {

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

21

const struct __base *base;

drivers/net/wireless/ralink/rt2x00/rt2x00queue.c

1113

#define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \

drivers/net/wireless/ralink/rt2x00/rt2x00queue.c

1114

(((char *)(__base)) + ((__limit) * (__esize)) + \

drivers/thermal/mediatek/lvts_thermal.c

24

#define LVTS_MONCTL0(__base) (__base + 0x0000)

drivers/thermal/mediatek/lvts_thermal.c

25

#define LVTS_MONCTL1(__base) (__base + 0x0004)

drivers/thermal/mediatek/lvts_thermal.c

26

#define LVTS_MONCTL2(__base) (__base + 0x0008)

drivers/thermal/mediatek/lvts_thermal.c

27

#define LVTS_MONINT(__base) (__base + 0x000C)

drivers/thermal/mediatek/lvts_thermal.c

28

#define LVTS_MONINTSTS(__base) (__base + 0x0010)

drivers/thermal/mediatek/lvts_thermal.c

29

#define LVTS_MONIDET0(__base) (__base + 0x0014)

drivers/thermal/mediatek/lvts_thermal.c

30

#define LVTS_MONIDET1(__base) (__base + 0x0018)

drivers/thermal/mediatek/lvts_thermal.c

31

#define LVTS_MONIDET2(__base) (__base + 0x001C)

drivers/thermal/mediatek/lvts_thermal.c

32

#define LVTS_MONIDET3(__base) (__base + 0x0020)

drivers/thermal/mediatek/lvts_thermal.c

33

#define LVTS_H2NTHRE(__base) (__base + 0x0024)

drivers/thermal/mediatek/lvts_thermal.c

34

#define LVTS_HTHRE(__base) (__base + 0x0028)

drivers/thermal/mediatek/lvts_thermal.c

35

#define LVTS_OFFSETH(__base) (__base + 0x0030)

drivers/thermal/mediatek/lvts_thermal.c

36

#define LVTS_OFFSETL(__base) (__base + 0x0034)

drivers/thermal/mediatek/lvts_thermal.c

37

#define LVTS_MSRCTL0(__base) (__base + 0x0038)

drivers/thermal/mediatek/lvts_thermal.c

38

#define LVTS_MSRCTL1(__base) (__base + 0x003C)

drivers/thermal/mediatek/lvts_thermal.c

39

#define LVTS_TSSEL(__base) (__base + 0x0040)

drivers/thermal/mediatek/lvts_thermal.c

40

#define LVTS_CALSCALE(__base) (__base + 0x0048)

drivers/thermal/mediatek/lvts_thermal.c

41

#define LVTS_ID(__base) (__base + 0x004C)

drivers/thermal/mediatek/lvts_thermal.c

42

#define LVTS_CONFIG(__base) (__base + 0x0050)

drivers/thermal/mediatek/lvts_thermal.c

43

#define LVTS_EDATA00(__base) (__base + 0x0054)

drivers/thermal/mediatek/lvts_thermal.c

44

#define LVTS_EDATA01(__base) (__base + 0x0058)

drivers/thermal/mediatek/lvts_thermal.c

45

#define LVTS_EDATA02(__base) (__base + 0x005C)

drivers/thermal/mediatek/lvts_thermal.c

46

#define LVTS_EDATA03(__base) (__base + 0x0060)

drivers/thermal/mediatek/lvts_thermal.c

47

#define LVTS_MSROFT(__base) (__base + 0x006C)

drivers/thermal/mediatek/lvts_thermal.c

48

#define LVTS_ATP0(__base) (__base + 0x0070)

drivers/thermal/mediatek/lvts_thermal.c

49

#define LVTS_ATP1(__base) (__base + 0x0074)

drivers/thermal/mediatek/lvts_thermal.c

50

#define LVTS_ATP2(__base) (__base + 0x0078)

drivers/thermal/mediatek/lvts_thermal.c

51

#define LVTS_ATP3(__base) (__base + 0x007C)

drivers/thermal/mediatek/lvts_thermal.c

52

#define LVTS_MSR0(__base) (__base + 0x0090)

drivers/thermal/mediatek/lvts_thermal.c

53

#define LVTS_MSR1(__base) (__base + 0x0094)

drivers/thermal/mediatek/lvts_thermal.c

54

#define LVTS_MSR2(__base) (__base + 0x0098)

drivers/thermal/mediatek/lvts_thermal.c

55

#define LVTS_MSR3(__base) (__base + 0x009C)

drivers/thermal/mediatek/lvts_thermal.c

56

#define LVTS_IMMD0(__base) (__base + 0x00A0)

drivers/thermal/mediatek/lvts_thermal.c

57

#define LVTS_IMMD1(__base) (__base + 0x00A4)

drivers/thermal/mediatek/lvts_thermal.c

58

#define LVTS_IMMD2(__base) (__base + 0x00A8)

drivers/thermal/mediatek/lvts_thermal.c

59

#define LVTS_IMMD3(__base) (__base + 0x00AC)

drivers/thermal/mediatek/lvts_thermal.c

60

#define LVTS_PROTCTL(__base) (__base + 0x00C0)

drivers/thermal/mediatek/lvts_thermal.c

61

#define LVTS_PROTTA(__base) (__base + 0x00C4)

drivers/thermal/mediatek/lvts_thermal.c

62

#define LVTS_PROTTB(__base) (__base + 0x00C8)

drivers/thermal/mediatek/lvts_thermal.c

63

#define LVTS_PROTTC(__base) (__base + 0x00CC)

drivers/thermal/mediatek/lvts_thermal.c

64

#define LVTS_CLKEN(__base) (__base + 0x00E4)

drivers/watchdog/s32g_wdt.c

20

#define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */

drivers/watchdog/s32g_wdt.c

26

#define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */

drivers/watchdog/s32g_wdt.c

28

#define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */

drivers/watchdog/s32g_wdt.c

32

#define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */

include/asm-generic/div64.h

181

uint32_t __base = (base); \

include/asm-generic/div64.h

184

if (__builtin_constant_p(__base) && \

include/asm-generic/div64.h

185

is_power_of_2(__base)) { \

include/asm-generic/div64.h

186

__rem = (n) & (__base - 1); \

include/asm-generic/div64.h

187

(n) >>= ilog2(__base); \

include/asm-generic/div64.h

188

} else if (__builtin_constant_p(__base) && \

include/asm-generic/div64.h

189

__base != 0) { \

include/asm-generic/div64.h

191

(n) = __div64_const32(n, __base); \

include/asm-generic/div64.h

194

__rem = __n_lo - __res_lo * __base; \

include/asm-generic/div64.h

196

__rem = (uint32_t)(n) % __base; \

include/asm-generic/div64.h

197

(n) = (uint32_t)(n) / __base; \

include/asm-generic/div64.h

199

__rem = __div64_32(&(n), __base); \

include/asm-generic/div64.h

46

uint32_t __base = (base); \

include/asm-generic/div64.h

48

__rem = ((uint64_t)(n)) % __base; \

include/asm-generic/div64.h

49

(n) = ((uint64_t)(n)) / __base; \

include/net/netfilter/nf_tables_offload.h

101

#define NFT_OFFLOAD_MATCH_EXACT(__key, __base, __field, __len, __reg) \

include/net/netfilter/nf_tables_offload.h

102

NFT_OFFLOAD_MATCH(__key, __base, __field, __len, __reg) \

include/net/netfilter/nf_tables_offload.h

89

#define NFT_OFFLOAD_MATCH_FLAGS(__key, __base, __field, __len, __reg, __flags) \

include/net/netfilter/nf_tables_offload.h

91

offsetof(struct nft_flow_key, __base); \

include/net/netfilter/nf_tables_offload.h

93

offsetof(struct nft_flow_key, __base.__field); \

include/net/netfilter/nf_tables_offload.h

98

#define NFT_OFFLOAD_MATCH(__key, __base, __field, __len, __reg) \

include/net/netfilter/nf_tables_offload.h

99

NFT_OFFLOAD_MATCH_FLAGS(__key, __base, __field, __len, __reg, 0)

tools/sched_ext/include/scx/common.bpf.h

260

u64 __base = (u64)&(base); \

tools/sched_ext/include/scx/common.bpf.h

261

u64 __addr = (u64)&((base) member) - __base; \

tools/sched_ext/include/scx/common.bpf.h

270

: "r"(__base), \

tools/sched_ext/include/scx/common.bpf.h

293

u64 __base = (u64)arr; \

tools/sched_ext/include/scx/common.bpf.h

294

u64 __addr = (u64)&(arr[i]) - __base; \

tools/sched_ext/include/scx/common.bpf.h

301

: "r"(__base), \