__dw_regs
return &__dw_regs(dw)->type.unroll.ch[ch].wr;
return &__dw_regs(dw)->type.unroll.ch[ch].rd;
&(__dw_regs(dw)->type.legacy.viewport_sel));
&(__dw_regs(dw)->type.legacy.viewport_sel));
writel(value, &(__dw_regs(dw)->name))
readl(&(__dw_regs(dw)->name))
writeq(value, &(__dw_regs(dw)->name))
readq(&(__dw_regs(dw)->name))
writel(value, &(__dw_regs(dw)->type.unroll.name))
return &(__dw_regs(dw)->type.legacy.ch);
return &(__dw_regs(dw)->ch[ch].wr);
return &(__dw_regs(dw)->ch[ch].rd);
dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
void __iomem *misc = __dw_regs(dw);
readl(&(__dw_regs(dw)->name))
writel((val), &(__dw_regs(dw)->name))
hi_lo_readq(&(__dw_regs(dw)->name))
hi_lo_writeq((val), &(__dw_regs(dw)->name))
writel(0x0, &(__dw_regs(dw)->status));
writel(BURST_REPEAT | BURST_VALUE, &(__dw_regs(dw)->burst_cnt));
writel(PATTERN_VALUE, &(__dw_regs(dw)->pattern));
writel(control, &(__dw_regs(dw)->control));
status = readl(&(__dw_regs(dw)->status));
*data = readl(&(__dw_regs(dw)->wr_cnt_msb));
*data |= readl(&(__dw_regs(dw)->wr_cnt_lsb));
*data = readl(&(__dw_regs(dw)->rd_cnt_msb));
*data |= readl(&(__dw_regs(dw)->rd_cnt_lsb));
writel(0x0, &(__dw_regs(dw)->perf_control));
writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
writel(0x0, &(__dw_regs(dw)->perf_control));
writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
writel(0x0, &(__dw_regs(dw)->RAM_addr));
writel(0x0, &(__dw_regs(dw)->RAM_port));
writel(lower_32_bits(addr), &(__dw_regs(dw)->addr_lsb));
writel(upper_32_bits(addr), &(__dw_regs(dw)->addr_msb));
burst = readl(&(__dw_regs(dw)->burst_cnt));
writel(burst, &(__dw_regs(dw)->burst_cnt));