drivers/gpu/drm/xe/instructions/xe_mi_commands.h

24

#define MI_NOOP __MI_INSTR(0x0)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

25

#define MI_USER_INTERRUPT __MI_INSTR(0x2)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

26

#define MI_ARB_CHECK __MI_INSTR(0x5)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

28

#define MI_ARB_ON_OFF __MI_INSTR(0x8)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

32

#define MI_BATCH_BUFFER_END __MI_INSTR(0xA)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

33

#define MI_TOPOLOGY_FILTER __MI_INSTR(0xD)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

34

#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

35

#define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

37

#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

50

#define MI_STORE_DATA_IMM __MI_INSTR(0x20)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

57

#define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

64

#define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

68

#define MI_FLUSH_DW __MI_INSTR(0x26)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

79

#define MI_LOAD_REGISTER_MEM (__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

83

#define MI_LOAD_REGISTER_REG (__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

87

#define MI_COPY_MEM_MEM (__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

91

#define MI_BATCH_BUFFER_START __MI_INSTR(0x31)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

93

#define MI_SET_APPID __MI_INSTR(0x0e)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

97

#define MI_SEMAPHORE_WAIT_TOKEN (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */