__REG - Linux

arch/arm/mach-pxa/pxa-regs.h

40

(*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))

arch/arm/mach-pxa/pxa27x-udc.h

106

#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */

arch/arm/mach-pxa/pxa27x-udc.h

11

#define UDCCR __REG(0x40600000) /* UDC Control Register */

arch/arm/mach-pxa/pxa27x-udc.h

116

#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */

arch/arm/mach-pxa/pxa27x-udc.h

117

#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */

arch/arm/mach-pxa/pxa27x-udc.h

118

#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */

arch/arm/mach-pxa/pxa27x-udc.h

119

#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */

arch/arm/mach-pxa/pxa27x-udc.h

120

#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */

arch/arm/mach-pxa/pxa27x-udc.h

121

#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */

arch/arm/mach-pxa/pxa27x-udc.h

122

#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */

arch/arm/mach-pxa/pxa27x-udc.h

123

#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */

arch/arm/mach-pxa/pxa27x-udc.h

124

#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */

arch/arm/mach-pxa/pxa27x-udc.h

125

#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */

arch/arm/mach-pxa/pxa27x-udc.h

126

#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */

arch/arm/mach-pxa/pxa27x-udc.h

127

#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */

arch/arm/mach-pxa/pxa27x-udc.h

128

#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */

arch/arm/mach-pxa/pxa27x-udc.h

129

#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */

arch/arm/mach-pxa/pxa27x-udc.h

130

#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */

arch/arm/mach-pxa/pxa27x-udc.h

131

#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */

arch/arm/mach-pxa/pxa27x-udc.h

132

#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */

arch/arm/mach-pxa/pxa27x-udc.h

133

#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */

arch/arm/mach-pxa/pxa27x-udc.h

134

#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */

arch/arm/mach-pxa/pxa27x-udc.h

135

#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */

arch/arm/mach-pxa/pxa27x-udc.h

136

#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */

arch/arm/mach-pxa/pxa27x-udc.h

137

#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */

arch/arm/mach-pxa/pxa27x-udc.h

138

#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */

arch/arm/mach-pxa/pxa27x-udc.h

153

#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */

arch/arm/mach-pxa/pxa27x-udc.h

154

#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */

arch/arm/mach-pxa/pxa27x-udc.h

155

#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */

arch/arm/mach-pxa/pxa27x-udc.h

156

#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */

arch/arm/mach-pxa/pxa27x-udc.h

157

#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */

arch/arm/mach-pxa/pxa27x-udc.h

158

#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */

arch/arm/mach-pxa/pxa27x-udc.h

159

#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */

arch/arm/mach-pxa/pxa27x-udc.h

160

#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */

arch/arm/mach-pxa/pxa27x-udc.h

161

#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */

arch/arm/mach-pxa/pxa27x-udc.h

162

#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */

arch/arm/mach-pxa/pxa27x-udc.h

163

#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */

arch/arm/mach-pxa/pxa27x-udc.h

164

#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */

arch/arm/mach-pxa/pxa27x-udc.h

165

#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */

arch/arm/mach-pxa/pxa27x-udc.h

166

#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */

arch/arm/mach-pxa/pxa27x-udc.h

167

#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */

arch/arm/mach-pxa/pxa27x-udc.h

168

#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */

arch/arm/mach-pxa/pxa27x-udc.h

169

#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */

arch/arm/mach-pxa/pxa27x-udc.h

170

#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */

arch/arm/mach-pxa/pxa27x-udc.h

171

#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */

arch/arm/mach-pxa/pxa27x-udc.h

172

#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */

arch/arm/mach-pxa/pxa27x-udc.h

173

#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */

arch/arm/mach-pxa/pxa27x-udc.h

174

#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */

arch/arm/mach-pxa/pxa27x-udc.h

175

#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */

arch/arm/mach-pxa/pxa27x-udc.h

176

#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */

arch/arm/mach-pxa/pxa27x-udc.h

181

#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */

arch/arm/mach-pxa/pxa27x-udc.h

182

#define UDCDRA __REG(0x40600304) /* Data Register - EPA */

arch/arm/mach-pxa/pxa27x-udc.h

183

#define UDCDRB __REG(0x40600308) /* Data Register - EPB */

arch/arm/mach-pxa/pxa27x-udc.h

184

#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */

arch/arm/mach-pxa/pxa27x-udc.h

185

#define UDCDRD __REG(0x40600310) /* Data Register - EPD */

arch/arm/mach-pxa/pxa27x-udc.h

186

#define UDCDRE __REG(0x40600314) /* Data Register - EPE */

arch/arm/mach-pxa/pxa27x-udc.h

187

#define UDCDRF __REG(0x40600318) /* Data Register - EPF */

arch/arm/mach-pxa/pxa27x-udc.h

188

#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */

arch/arm/mach-pxa/pxa27x-udc.h

189

#define UDCDRH __REG(0x40600320) /* Data Register - EPH */

arch/arm/mach-pxa/pxa27x-udc.h

190

#define UDCDRI __REG(0x40600324) /* Data Register - EPI */

arch/arm/mach-pxa/pxa27x-udc.h

191

#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */

arch/arm/mach-pxa/pxa27x-udc.h

192

#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */

arch/arm/mach-pxa/pxa27x-udc.h

193

#define UDCDRL __REG(0x40600330) /* Data Register - EPL */

arch/arm/mach-pxa/pxa27x-udc.h

194

#define UDCDRM __REG(0x40600334) /* Data Register - EPM */

arch/arm/mach-pxa/pxa27x-udc.h

195

#define UDCDRN __REG(0x40600338) /* Data Register - EPN */

arch/arm/mach-pxa/pxa27x-udc.h

196

#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */

arch/arm/mach-pxa/pxa27x-udc.h

197

#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */

arch/arm/mach-pxa/pxa27x-udc.h

198

#define UDCDRR __REG(0x40600344) /* Data Register - EPR */

arch/arm/mach-pxa/pxa27x-udc.h

199

#define UDCDRS __REG(0x40600348) /* Data Register - EPS */

arch/arm/mach-pxa/pxa27x-udc.h

200

#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */

arch/arm/mach-pxa/pxa27x-udc.h

201

#define UDCDRU __REG(0x40600350) /* Data Register - EPU */

arch/arm/mach-pxa/pxa27x-udc.h

202

#define UDCDRV __REG(0x40600354) /* Data Register - EPV */

arch/arm/mach-pxa/pxa27x-udc.h

203

#define UDCDRW __REG(0x40600358) /* Data Register - EPW */

arch/arm/mach-pxa/pxa27x-udc.h

204

#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */

arch/arm/mach-pxa/pxa27x-udc.h

207

#define UDCCRA __REG(0x40600404) /* Configuration register EPA */

arch/arm/mach-pxa/pxa27x-udc.h

208

#define UDCCRB __REG(0x40600408) /* Configuration register EPB */

arch/arm/mach-pxa/pxa27x-udc.h

209

#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */

arch/arm/mach-pxa/pxa27x-udc.h

210

#define UDCCRD __REG(0x40600410) /* Configuration register EPD */

arch/arm/mach-pxa/pxa27x-udc.h

211

#define UDCCRE __REG(0x40600414) /* Configuration register EPE */

arch/arm/mach-pxa/pxa27x-udc.h

212

#define UDCCRF __REG(0x40600418) /* Configuration register EPF */

arch/arm/mach-pxa/pxa27x-udc.h

213

#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */

arch/arm/mach-pxa/pxa27x-udc.h

214

#define UDCCRH __REG(0x40600420) /* Configuration register EPH */

arch/arm/mach-pxa/pxa27x-udc.h

215

#define UDCCRI __REG(0x40600424) /* Configuration register EPI */

arch/arm/mach-pxa/pxa27x-udc.h

216

#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */

arch/arm/mach-pxa/pxa27x-udc.h

217

#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */

arch/arm/mach-pxa/pxa27x-udc.h

218

#define UDCCRL __REG(0x40600430) /* Configuration register EPL */

arch/arm/mach-pxa/pxa27x-udc.h

219

#define UDCCRM __REG(0x40600434) /* Configuration register EPM */

arch/arm/mach-pxa/pxa27x-udc.h

220

#define UDCCRN __REG(0x40600438) /* Configuration register EPN */

arch/arm/mach-pxa/pxa27x-udc.h

221

#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */

arch/arm/mach-pxa/pxa27x-udc.h

222

#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */

arch/arm/mach-pxa/pxa27x-udc.h

223

#define UDCCRR __REG(0x40600444) /* Configuration register EPR */

arch/arm/mach-pxa/pxa27x-udc.h

224

#define UDCCRS __REG(0x40600448) /* Configuration register EPS */

arch/arm/mach-pxa/pxa27x-udc.h

225

#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */

arch/arm/mach-pxa/pxa27x-udc.h

226

#define UDCCRU __REG(0x40600450) /* Configuration register EPU */

arch/arm/mach-pxa/pxa27x-udc.h

227

#define UDCCRV __REG(0x40600454) /* Configuration register EPV */

arch/arm/mach-pxa/pxa27x-udc.h

228

#define UDCCRW __REG(0x40600458) /* Configuration register EPW */

arch/arm/mach-pxa/pxa27x-udc.h

229

#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */

arch/arm/mach-pxa/pxa27x-udc.h

35

#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */

arch/arm/mach-pxa/pxa27x-udc.h

36

#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */

arch/arm/mach-pxa/pxa27x-udc.h

50

#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */

arch/arm/mach-pxa/pxa27x-udc.h

51

#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */

arch/arm/mach-pxa/pxa27x-udc.h

59

#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */

arch/arm/mach-pxa/pxa27x-udc.h

60

#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */

arch/arm/mach-pxa/pxa27x-udc.h

87

#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */

arch/arm/mach-pxa/pxa27x-udc.h

88

#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */

arch/arm/mach-pxa/pxa27x.h

11

#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */

arch/arm/mach-pxa/pxa2xx-regs.h

20

#define PMCR __REG(0x40F00000) /* Power Manager Control Register */

arch/arm/mach-pxa/pxa2xx-regs.h

21

#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */

arch/arm/mach-pxa/pxa2xx-regs.h

22

#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */

arch/arm/mach-pxa/pxa2xx-regs.h

23

#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */

arch/arm/mach-pxa/pxa2xx-regs.h

24

#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */

arch/arm/mach-pxa/pxa2xx-regs.h

25

#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */

arch/arm/mach-pxa/pxa2xx-regs.h

26

#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */

arch/arm/mach-pxa/pxa2xx-regs.h

27

#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */

arch/arm/mach-pxa/pxa2xx-regs.h

28

#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */

arch/arm/mach-pxa/pxa2xx-regs.h

29

#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */

arch/arm/mach-pxa/pxa2xx-regs.h

30

#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */

arch/arm/mach-pxa/pxa2xx-regs.h

31

#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */

arch/arm/mach-pxa/pxa2xx-regs.h

32

#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */

arch/arm/mach-pxa/pxa2xx-regs.h

34

#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */

arch/arm/mach-pxa/pxa2xx-regs.h

35

#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */

arch/arm/mach-pxa/pxa2xx-regs.h

36

#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */

arch/arm/mach-pxa/pxa2xx-regs.h

37

#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */

arch/arm/mach-pxa/pxa2xx-regs.h

38

#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */

arch/arm/mach-pxa/pxa2xx-regs.h

39

#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */

arch/arm/mach-pxa/pxa2xx-regs.h

41

#define PCMD0 __REG(0x40F00080 + 0 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

42

#define PCMD1 __REG(0x40F00080 + 1 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

43

#define PCMD2 __REG(0x40F00080 + 2 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

44

#define PCMD3 __REG(0x40F00080 + 3 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

45

#define PCMD4 __REG(0x40F00080 + 4 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

46

#define PCMD5 __REG(0x40F00080 + 5 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

47

#define PCMD6 __REG(0x40F00080 + 6 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

48

#define PCMD7 __REG(0x40F00080 + 7 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

49

#define PCMD8 __REG(0x40F00080 + 8 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

50

#define PCMD9 __REG(0x40F00080 + 9 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

51

#define PCMD10 __REG(0x40F00080 + 10 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

52

#define PCMD11 __REG(0x40F00080 + 11 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

53

#define PCMD12 __REG(0x40F00080 + 12 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

54

#define PCMD13 __REG(0x40F00080 + 13 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

55

#define PCMD14 __REG(0x40F00080 + 14 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

56

#define PCMD15 __REG(0x40F00080 + 15 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

57

#define PCMD16 __REG(0x40F00080 + 16 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

58

#define PCMD17 __REG(0x40F00080 + 17 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

59

#define PCMD18 __REG(0x40F00080 + 18 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

60

#define PCMD19 __REG(0x40F00080 + 19 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

61

#define PCMD20 __REG(0x40F00080 + 20 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

62

#define PCMD21 __REG(0x40F00080 + 21 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

63

#define PCMD22 __REG(0x40F00080 + 22 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

64

#define PCMD23 __REG(0x40F00080 + 23 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

65

#define PCMD24 __REG(0x40F00080 + 24 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

66

#define PCMD25 __REG(0x40F00080 + 25 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

67

#define PCMD26 __REG(0x40F00080 + 26 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

68

#define PCMD27 __REG(0x40F00080 + 27 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

69

#define PCMD28 __REG(0x40F00080 + 28 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

70

#define PCMD29 __REG(0x40F00080 + 29 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

71

#define PCMD30 __REG(0x40F00080 + 30 * 4)

arch/arm/mach-pxa/pxa2xx-regs.h

72

#define PCMD31 __REG(0x40F00080 + 31 * 4)

arch/arm/mach-pxa/pxa3xx-regs.h

126

#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */

arch/arm/mach-pxa/pxa3xx-regs.h

127

#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */

arch/arm/mach-pxa/pxa3xx-regs.h

128

#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */

arch/arm/mach-pxa/pxa3xx-regs.h

129

#define CKENA __REG(0x4134000C) /* A Clock Enable Register */

arch/arm/mach-pxa/pxa3xx-regs.h

130

#define CKENB __REG(0x41340010) /* B Clock Enable Register */

arch/arm/mach-pxa/pxa3xx-regs.h

131

#define CKENC __REG(0x41340024) /* C Clock Enable Register */

arch/arm/mach-pxa/pxa3xx-regs.h

132

#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */

arch/arm/mach-pxa/pxa3xx-regs.h

26

#define PMCR __REG(0x40F50000) /* Power Manager Control Register */

arch/arm/mach-pxa/pxa3xx-regs.h

27

#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */

arch/arm/mach-pxa/pxa3xx-regs.h

28

#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */

arch/arm/mach-pxa/pxa3xx-regs.h

29

#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */

arch/arm/mach-pxa/pxa3xx-regs.h

30

#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */

arch/arm/mach-pxa/pxa3xx-regs.h

31

#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */

arch/arm/mach-pxa/pxa3xx-regs.h

32

#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */

arch/arm/mach-pxa/pxa3xx-regs.h

33

#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */

arch/arm/mach-pxa/pxa3xx-regs.h

34

#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */

arch/arm/mach-pxa/pxa3xx-regs.h

35

#define PCMD(x) __REG(0x40F50110 + ((x) << 2))

arch/arm/mach-pxa/pxa3xx-regs.h

40

#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */

arch/arm/mach-pxa/pxa3xx-regs.h

41

#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */

arch/arm/mach-pxa/pxa3xx-regs.h

42

#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */

arch/arm/mach-pxa/pxa3xx-regs.h

43

#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */

arch/arm/mach-pxa/pxa3xx-regs.h

44

#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */

arch/arm/mach-pxa/pxa3xx-regs.h

45

#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */

arch/arm/mach-pxa/pxa3xx-regs.h

46

#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */

arch/arm/mach-pxa/pxa3xx-regs.h

47

#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */

arch/arm/mach-pxa/pxa3xx-regs.h

48

#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */

arch/arm/mach-pxa/pxa3xx-regs.h

49

#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */

arch/arm/mach-pxa/pxa3xx-regs.h

50

#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */

arch/arm/mach-pxa/pxa3xx-regs.h

51

#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */

arch/arm/mach-pxa/pxa3xx-regs.h

52

#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */

arch/arm/mach-pxa/pxa3xx-regs.h

53

#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */

arch/arm/mach-pxa/regs-rtc.h

11

#define RCNR __REG(0x40900000) /* RTC Count Register */

arch/arm/mach-pxa/regs-rtc.h

12

#define RTAR __REG(0x40900004) /* RTC Alarm Register */

arch/arm/mach-pxa/regs-rtc.h

13

#define RTSR __REG(0x40900008) /* RTC Status Register */

arch/arm/mach-pxa/regs-rtc.h

14

#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */

arch/arm/mach-pxa/regs-rtc.h

15

#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1025

#define RSRR __REG(0x90030000) /* RC Software Reset Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1026

#define RCSR __REG(0x90030004) /* RC Status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1043

#define TUCR __REG(0x90030008) /* Test Unit Control Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1105

#define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1106

#define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1107

#define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1108

#define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1109

#define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

111

#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1110

#define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1111

#define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1112

#define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

112

#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

113

#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

114

#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

115

#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

116

#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */

arch/arm/mach-sa1100/include/mach/SA-1100.h

117

#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */

arch/arm/mach-sa1100/include/mach/SA-1100.h

118

#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

119

#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

120

#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

121

#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1210

#define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1211

#define ICMR __REG(0x90050004) /* IC Mask Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1212

#define ICLR __REG(0x90050008) /* IC Level Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1213

#define ICCR __REG(0x9005000C) /* IC Control Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1214

#define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1215

#define ICPR __REG(0x90050020) /* IC Pending Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1283

#define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1284

#define PPSR __REG(0x90060004) /* PPC Pin State Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1285

#define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1286

#define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1287

#define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1368

#define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1369

#define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1370

#define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1371

#define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1443

#define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1444

#define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1445

#define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1513

#define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

1541

#define MDREFR __REG(0xA000001C)

arch/arm/mach-sa1100/include/mach/SA-1100.h

267

#define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

268

#define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

269

#define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

270

#define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

271

#define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

272

#define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

273

#define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

274

#define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */

arch/arm/mach-sa1100/include/mach/SA-1100.h

429

#define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

430

#define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

431

#define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

432

#define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

433

#define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

434

#define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

435

#define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

436

#define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

543

#define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

544

#define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

545

#define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

546

#define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

547

#define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

548

#define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

630

#define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

631

#define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */

arch/arm/mach-sa1100/include/mach/SA-1100.h

632

#define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */

arch/arm/mach-sa1100/include/mach/SA-1100.h

633

#define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */

arch/arm/mach-sa1100/include/mach/SA-1100.h

634

#define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

635

#define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

753

#define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

754

#define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */

arch/arm/mach-sa1100/include/mach/SA-1100.h

755

#define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

756

#define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

884

#define PMCR __REG(0x90020000) /* PM Control Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

885

#define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

886

#define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

887

#define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

888

#define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

889

#define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

890

#define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */

arch/arm/mach-sa1100/include/mach/SA-1100.h

891

#define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */

arch/xtensa/include/asm/coprocessor.h

102

__REG ## list (cc, abi, type, name, size, align)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1013

#define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1028

#define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1031

#define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

104

#define ANA_EMIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1040

#define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1043

#define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1046

#define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1055

#define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1064

#define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1079

#define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1082

#define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1109

#define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1118

#define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1121

#define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

113

#define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1130

#define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1138

#define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1146

#define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1179

#define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1188

#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1203

#define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1206

#define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1209

#define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1212

#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1227

#define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1230

#define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1257

#define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1272

#define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1281

#define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1314

#define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1323

#define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1326

#define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1329

#define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

134

#define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1344

#define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1370

#define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1379

#define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1406

#define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1415

#define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1424

#define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1439

#define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1448

#define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1451

#define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1460

#define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1463

#define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1472

#define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1481

#define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1490

#define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1511

#define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1526

#define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1529

#define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1538

#define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1553

#define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1580

#define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1595

#define REW_DSCP_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1604

#define REW_PCP_DEI_CFG(g, r) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 16, r, 16, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

161

#define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1619

#define REW_STAT_CFG __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528, 520, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1628

#define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1637

#define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1652

#define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1661

#define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1670

#define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1679

#define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

170

#define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1700

#define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1703

#define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1706

#define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1745

#define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1748

#define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1757

#define VCAP_UPDATE_CTRL(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

179

#define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1808

#define VCAP_MV_CFG(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

182

#define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1823

#define VCAP_ENTRY_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1826

#define VCAP_MASK_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1829

#define VCAP_ACTION_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1832

#define VCAP_CNT_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1835

#define VCAP_CNT_FW_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1838

#define VCAP_TG_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1841

#define VCAP_CORE_IDX(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

185

#define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1850

#define VCAP_CORE_MAP(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1859

#define VCAP_VER(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1862

#define VCAP_ENTRY_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1865

#define VCAP_ENTRY_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1868

#define VCAP_ENTRY_SWCNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1871

#define VCAP_ENTRY_TG_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1874

#define VCAP_ACTION_DEF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1877

#define VCAP_ACTION_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1880

#define VCAP_CNT_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1883

#define VCAP_CORE_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

1886

#define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

224

#define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

239

#define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

248

#define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

257

#define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

272

#define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

305

#define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

332

#define ANA_QOS_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

35

#define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

365

#define ANA_VCAP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

374

#define ANA_VCAP_S1_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 16, r, 3, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

401

#define ANA_VCAP_S2_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

44

#define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

464

#define ANA_PCP_DEI_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 32, r, 16, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

479

#define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

506

#define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

509

#define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

542

#define ANA_DSCP_REWR_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 332, r, 16, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

551

#define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

566

#define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

575

#define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

59

#define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

620

#define ANA_DSCP_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 76, r, 64, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

647

#define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

662

#define ANA_POL_MODE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

68

#define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

695

#define ANA_POL_PIR_STATE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

704

#define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

71

#define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

713

#define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

752

#define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

767

#define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

776

#define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

785

#define DEV_MAC_TAGS_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

800

#define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

821

#define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

836

#define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

839

#define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

842

#define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

851

#define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

86

#define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

866

#define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

875

#define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

902

#define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

917

#define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

932

#define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

941

#define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

95

#define ANA_MIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

950

#define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

959

#define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

968

#define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

977

#define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

980

#define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

983

#define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4)

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

986

#define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1012

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1024

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1035

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1052

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

106

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1064

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1075

__REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1099

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1110

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1127

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1146

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1169

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1181

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1204

__REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1257

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1280

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1351

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1368

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1439

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1450

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1467

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

147

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

153

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1544

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1549

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1566

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

159

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1613

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1624

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1659

__REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1670

__REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

170

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1747

__REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1753

__REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1759

__REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

176

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1770

__REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1782

__REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1794

__REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1806

__REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1817

__REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

182

__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1876

__REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1882

__REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\

drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

1888

__REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\