__GENMASK
#define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
#define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
#define KVM_ASYNC_PF_VEC_MASK __GENMASK(7, 0)
#define GENMASK(h, l) __GENMASK(h, l)
#define PCI_IDE_CAP_ALG __GENMASK(12, 8) /* Supported Algorithms */
#define PCI_IDE_CAP_LINK_TC_NUM __GENMASK(15, 13) /* Link IDE TCs */
#define PCI_IDE_CAP_SEL_NUM __GENMASK(23, 16) /* Supported Selective IDE Streams */
#define PCI_IDE_LINK_CTL_TX_AGGR_NPR __GENMASK(3, 2) /* Tx Aggregation Mode NPR */
#define PCI_IDE_LINK_CTL_TX_AGGR_PR __GENMASK(5, 4) /* Tx Aggregation Mode PR */
#define PCI_IDE_LINK_CTL_TX_AGGR_CPL __GENMASK(7, 6) /* Tx Aggregation Mode CPL */
#define PCI_IDE_LINK_CTL_PART_ENC __GENMASK(13, 10) /* Partial Header Encryption Mode */
#define PCI_IDE_LINK_CTL_ALG __GENMASK(18, 14) /* Selection from PCI_IDE_CAP_ALG */
#define PCI_IDE_LINK_CTL_TC __GENMASK(21, 19) /* Traffic Class */
#define PCI_IDE_LINK_CTL_ID __GENMASK(31, 24) /* Stream ID */
#define PCI_IDE_LINK_STS_STATE __GENMASK(3, 0) /* Link IDE Stream State */
#define PCI_IDE_SEL_CAP_ASSOC_NUM __GENMASK(3, 0)
#define PCI_IDE_SEL_CTL_TX_AGGR_NPR __GENMASK(3, 2) /* Tx Aggregation Mode NPR */
#define PCI_IDE_SEL_CTL_TX_AGGR_PR __GENMASK(5, 4) /* Tx Aggregation Mode PR */
#define PCI_IDE_SEL_CTL_TX_AGGR_CPL __GENMASK(7, 6) /* Tx Aggregation Mode CPL */
#define PCI_IDE_SEL_CTL_PART_ENC __GENMASK(13, 10) /* Partial Header Encryption Mode */
#define PCI_IDE_SEL_CTL_ALG __GENMASK(18, 14) /* Selection from PCI_IDE_CAP_ALG */
#define PCI_IDE_SEL_CTL_TC __GENMASK(21, 19) /* Traffic Class */
#define PCI_IDE_SEL_CTL_ID __GENMASK(31, 24) /* Stream ID */
#define PCI_IDE_SEL_STS_STATE __GENMASK(3, 0) /* Selective IDE Stream State */
#define PCI_IDE_SEL_RID_1_LIMIT __GENMASK(23, 8)
#define PCI_IDE_SEL_RID_2_BASE __GENMASK(23, 8)
#define PCI_IDE_SEL_RID_2_SEG __GENMASK(31, 24)
#define PCI_IDE_SEL_ADDR_1_BASE_LOW __GENMASK(19, 8)
#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW __GENMASK(31, 20)
#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28)
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0)
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8)
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0)
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8)
#define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0)
#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8)
#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16)
#define VDSO_AUX __GENMASK(CLOCK_AUX_LAST, CLOCK_AUX)
KUNIT_EXPECT_EQ(test, 1ul, __GENMASK(0, 0));
KUNIT_EXPECT_EQ(test, 3ul, __GENMASK(1, 0));
KUNIT_EXPECT_EQ(test, 6ul, __GENMASK(2, 1));
KUNIT_EXPECT_EQ(test, 0xFFFFFFFFul, __GENMASK(31, 0));
#define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
#define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
#define GENMASK(h, l) __GENMASK(h, l)