__EVENT_CONSTRAINT
__EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK, 1, 0, PERF_X86_EVENT_PAIR);
__EVENT_CONSTRAINT(0, even_ctr_mask, 0,
__EVENT_CONSTRAINT(0, x86_pmu.cntr_mask64,
__EVENT_CONSTRAINT(0, pmu->cntr_mask64,
__EVENT_CONSTRAINT(0, pmu->cntr_mask64,
__EVENT_CONSTRAINT(0, pmu->cntr_mask64,
__EVENT_CONSTRAINT(INTEL_FIXED_VLBR_EVENT, (1ULL << INTEL_PMC_IDX_FIXED_VLBR),
__EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
__EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \
__EVENT_CONSTRAINT(code, n, \