drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

16

_PICK_EVEN_2RANGES(phy, 1, \

drivers/gpu/drm/i915/display/intel_color_regs.h

34

_PICK_EVEN_2RANGES(pipe, 2, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

118

#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

142

#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

166

#define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

183

#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

39

#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

60

#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

90

#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

65

#define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

drivers/gpu/drm/i915/display/intel_display_reg_defs.h

66

#define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

drivers/gpu/drm/i915/display/intel_display_regs.h

126

_MMIO(_PICK_EVEN_2RANGES(x, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2929

#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2935

#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2950

#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3011

#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3026

#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3034

#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3040

#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3047

#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

3053

#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \

drivers/gpu/drm/i915/display/intel_display_regs.h

39

_MMIO(_PICK_EVEN_2RANGES(phy, 1, \

drivers/gpu/drm/i915/display/intel_dmc_regs.h

371

_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \

drivers/gpu/drm/i915/display/intel_dp_aux_regs.h

38

_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \

drivers/gpu/drm/i915/display/intel_dp_aux_regs.h

92

_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

54

#define _XE3PLPD_PORT_BUF_CTL5(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

65

#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

145

#define _FIA(fia) _PICK_EVEN_2RANGES((fia), 1, \

drivers/gpu/drm/i915/display/skl_universal_plane_regs.h

21

_PICK_EVEN_2RANGES((plane), PLANE_5, \

drivers/gpu/drm/i915/gt/intel_gt_regs.h

366

#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \

drivers/gpu/drm/xe/xe_pat.c

24

#define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \