drivers/gpu/drm/i915/display/icl_dsi_regs.h

12

#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \

drivers/gpu/drm/i915/display/intel_audio_regs.h

100

#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)

drivers/gpu/drm/i915/display/intel_audio_regs.h

105

#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)

drivers/gpu/drm/i915/display/intel_audio_regs.h

110

#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)

drivers/gpu/drm/i915/display/intel_audio_regs.h

121

#define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL)

drivers/gpu/drm/i915/display/intel_audio_regs.h

85

#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)

drivers/gpu/drm/i915/display/intel_audio_regs.h

89

#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)

drivers/gpu/drm/i915/display/intel_audio_regs.h

93

#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

1691

#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \

drivers/gpu/drm/i915/display/intel_display_regs.h

2294

#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2304

#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2312

#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2316

#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2721

#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

107

#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

117

#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

127

#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

138

#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

149

#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

160

#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

198

#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

212

#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

223

#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

246

#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

263

#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

84

#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

96

#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_psr_regs.h

256

#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, _LNL_SFF_CTL_A, _LNL_SFF_CTL_B)

drivers/gpu/drm/i915/display/intel_psr_regs.h

261

#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, _LNL_CFF_CTL_A, _LNL_CFF_CTL_B)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

13

#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

23

#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

29

#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

38

#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

44

#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

53

#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

59

#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

67

#define TRANS_VRR_DCB_VMAX_LIVE(trans) _MMIO_TRANS(trans, \

drivers/gpu/drm/i915/display/intel_vrr_regs.h

73

#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \