arch/riscv/include/asm/asm.h

22

#define __REG_SEL(a, b) __ASM_STR(a)

arch/riscv/include/asm/asm.h

24

#define __REG_SEL(a, b) __ASM_STR(b)

arch/riscv/include/asm/asm.h

63

#define RISCV_INT __ASM_STR(.word)

arch/riscv/include/asm/asm.h

64

#define RISCV_SZINT __ASM_STR(4)

arch/riscv/include/asm/asm.h

65

#define RISCV_LGINT __ASM_STR(2)

arch/riscv/include/asm/asm.h

71

#define RISCV_SHORT __ASM_STR(.half)

arch/riscv/include/asm/asm.h

72

#define RISCV_SZSHORT __ASM_STR(2)

arch/riscv/include/asm/asm.h

73

#define RISCV_LGSHORT __ASM_STR(1)

arch/riscv/include/asm/csr.h

552

__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

561

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

arch/riscv/include/asm/csr.h

570

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/csr.h

578

__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

587

__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/csr.h

595

__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\

arch/riscv/include/asm/csr.h

604

__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \

arch/riscv/include/asm/insn-def.h

170

#define RV_OPCODE(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

171

#define RV_FUNC3(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

172

#define RV_FUNC7(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

173

#define RV_SIMM12(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

174

#define RV_RD(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

175

#define RV_RS1(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

176

#define RV_RS2(v) __ASM_STR(v)

arch/riscv/include/asm/insn-def.h

177

#define __RV_REG(v) __ASM_STR(x ## v)

arch/riscv/include/asm/insn-def.h

209

__ASM_STR(.error "hlv.d requires 64-bit support")

arch/riscv/include/asm/insn-def.h

278

__ASM_STR(.error "ld.aq requires 64-bit support")

arch/riscv/include/asm/insn-def.h

281

__ASM_STR(.error "ld.aqrl requires 64-bit support")

arch/riscv/include/asm/insn-def.h

284

__ASM_STR(.error "sd.rl requires 64-bit support")

arch/riscv/include/asm/insn-def.h

287

__ASM_STR(.error "sd.aqrl requires 64-bit support")

tools/arch/riscv/include/asm/csr.h

483

__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

492

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

tools/arch/riscv/include/asm/csr.h

501

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \

tools/arch/riscv/include/asm/csr.h

509

__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

518

__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \

tools/arch/riscv/include/asm/csr.h

526

__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\

tools/arch/riscv/include/asm/csr.h

535

__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

68

__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \

tools/testing/selftests/riscv/cfi/cfi_rv_test.h

77

__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \