arch/loongarch/include/asm/addrspace.h

23

#define PHYS_OFFSET _UL(0)

arch/loongarch/include/asm/addrspace.h

50

#define TO_PHYS_MASK ((_UL(1) << _UL(DMW_PABITS)) - 1)

arch/loongarch/include/asm/addrspace.h

60

#define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS))

arch/loongarch/include/asm/addrspace.h

89

#define _CONST64_(x) _UL(x)

arch/powerpc/include/asm/reg.h

900

#define MMCRA_BHRB_DISABLE _UL(0x2000000000) // BHRB disable bit for ISA v3.1

arch/riscv/include/asm/bug.h

15

#define __INSN_LENGTH_MASK _UL(0x3)

arch/riscv/include/asm/bug.h

16

#define __INSN_LENGTH_32 _UL(0x3)

arch/riscv/include/asm/bug.h

17

#define __COMPRESSED_INSN_MASK _UL(0xffff)

arch/riscv/include/asm/bug.h

19

#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */

arch/riscv/include/asm/bug.h

20

#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */

arch/riscv/include/asm/insn.h

231

#define __INSN_LENGTH_MASK _UL(0x3)

arch/riscv/include/asm/insn.h

232

#define __INSN_LENGTH_GE_32 _UL(0x3)

arch/riscv/include/asm/insn.h

233

#define __INSN_OPCODE_MASK _UL(0x7F)

arch/riscv/include/asm/insn.h

234

#define __INSN_BRANCH_OPCODE _UL(RVG_OPCODE_BRANCH)

arch/x86/include/asm/tdx.h

24

#define TDX_SEAMCALL_VMFAILINVALID (TDX_SW_ERROR | _UL(0xFFFF0000))

drivers/firmware/arm_scmi/transports/smc.c

39

#define SHMEM_PAGE(x) (_UL((x) >> SHMEM_SHIFT))

include/uapi/linux/bits.h

7

#define __GENMASK(h, l) (((~_UL(0)) << (l)) & (~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))

include/uapi/linux/const.h

28

#define _BITUL(x) (_UL(1) << (x))

include/vdso/const.h

7

#define UL(x) (_UL(x))

tools/include/uapi/linux/bits.h

7

#define __GENMASK(h, l) (((~_UL(0)) << (l)) & (~_UL(0) >> (__BITS_PER_LONG - 1 - (h))))

tools/include/uapi/linux/const.h

28

#define _BITUL(x) (_UL(1) << (x))

tools/include/vdso/const.h

7

#define UL(x) (_UL(x))