_SB_MAKEMASK1
#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4)
#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5)
#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6)
#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7)
#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8)
#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9)
#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36)
#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37)
#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38)
#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)
#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42)
#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43)
#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16)
#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0)
#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1)
#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2)
#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3)
#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4)
#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5)
#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6)
#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7)
#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8)
#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9)
#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10)
#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11)
#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12)
#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13)
#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14)
#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15)
#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16)
#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17)
#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18)
#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19)
#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20)
#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21)
#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22)
#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23)
#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24)
#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25)
#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26)
#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27)
#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28)
#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29)
#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30)
#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46)
#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63)
#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8)
#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9)
#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30)
#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31)
#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34)
#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35)
#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36)
#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37)
#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38)
#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39)
#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40)
#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41)
#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8)
#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62)
#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16)
#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29)
#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30)
#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32)
#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35)
#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60)
#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61)
#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62)
#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63)
#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19)
#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20)
#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21)
#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23)
#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24)
#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53)
#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54)
#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55)
#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60)
#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61)
#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62)
#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63)
#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8)
#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5)
#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14)
#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0)
#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1)
#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2)
#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3)
#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4)
#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57)
#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58)
#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
#define M_IO_COH_ERR _SB_MAKEMASK1(14)
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7)
#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6)
#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5)
#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4)
#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3)
#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36)
#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37)
#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38)
#define M_MAC_SS_EN _SB_MAKEMASK1(39)
#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
#define M_MAC_FC_SEL _SB_MAKEMASK1(54)
#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0)
#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1)
#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4)
#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5)
#define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8)
#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16)
#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24)
#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32)
#define M_MAC_RESERVED0 _SB_MAKEMASK1(0)
#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1)
#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
#define M_MAC_RETRY_EN _SB_MAKEMASK1(2)
#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3)
#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4)
#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
#define M_MAC_INT_HWM _SB_MAKEMASK1(3)
#define M_MAC_BURST_EN _SB_MAKEMASK1(5)
#define M_MAC_INT_LWM _SB_MAKEMASK1(4)
#define M_MAC_INT_DSCR _SB_MAKEMASK1(5)
#define M_MAC_INT_ERR _SB_MAKEMASK1(6)
#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */
#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */
#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41)
#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42)
#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43)
#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0)
#define M_MAC_UCAST_EN _SB_MAKEMASK1(1)
#define M_MAC_UCAST_INV _SB_MAKEMASK1(2)
#define M_MAC_MCAST_EN _SB_MAKEMASK1(3)
#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC)
#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR)
#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR)
#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT)
#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC)
#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN)
#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18)
#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22)
#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23)
#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
#define M_MAC_HDX_EN _SB_MAKEMASK1(33)
#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
#define M_MC_DEBUG _SB_MAKEMASK1(63)
#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
#define M_MC_CS0 _SB_MAKEMASK1(4)
#define M_MC_CS1 _SB_MAKEMASK1(5)
#define M_MC_CS2 _SB_MAKEMASK1(6)
#define M_MC_CS3 _SB_MAKEMASK1(7)
#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
#define M_tCrDh _SB_MAKEMASK1(7)
#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
#define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
#define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
#define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
#define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
#define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)
#define M_SMB_PEC _SB_MAKEMASK1(15)
#define M_SMB_EXTEND _SB_MAKEMASK1(14)
#define M_SMB_DIR _SB_MAKEMASK1(13)
#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7)
#define M_SMB_BUSY _SB_MAKEMASK1(0)
#define M_SMB_ERROR _SB_MAKEMASK1(1)
#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
#define M_SMB_QDATA _SB_MAKEMASK1(7)
#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9)
#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10)
#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11)
#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16)
#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17)
#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18)
#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19)
#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20)
#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21)
#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22)
#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24)
#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25)
#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26)
#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27)
#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28)
#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29)
#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30)
#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31)
#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0)
#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1)
#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6)
#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7)
#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0)
#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1)
#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6)
#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7)
#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8)
#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9)
#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0)
#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1)
#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4)
#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5)
#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6)
#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7)
#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8)
#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9)
#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12)
#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13)
#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14)
#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15)
#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0)
#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1)
#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2)
#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3)
#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5)
#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0)
#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4)
#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0)
#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1)
#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2)
#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3)
#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4)
#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5)
#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6)
#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8)
#define M_DUART_RX_EN _SB_MAKEMASK1(0)
#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
#define M_DUART_TX_EN _SB_MAKEMASK1(2)
#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */