arch/arm/mach-lpc32xx/lpc32xx.h

14

#define _BIT(n) _SBF(n, 1)

drivers/crypto/rockchip/rk3288_crypto.h

165

#define RK_CRYPTO_HASH_SHA1 _SBF(0x00, 0)

drivers/crypto/rockchip/rk3288_crypto.h

166

#define RK_CRYPTO_HASH_MD5 _SBF(0x01, 0)

drivers/crypto/rockchip/rk3288_crypto.h

167

#define RK_CRYPTO_HASH_SHA256 _SBF(0x02, 0)

drivers/crypto/rockchip/rk3288_crypto.h

168

#define RK_CRYPTO_HASH_PRNG _SBF(0x03, 0)

drivers/crypto/rockchip/rk3288_crypto.h

39

#define RK_CRYPTO_WRITE_MASK _SBF(0xFFFF, 16)

drivers/crypto/rockchip/rk3288_crypto.h

63

#define RK_CYYPTO_HASHINSEL_INDEPENDENT_SOURCE _SBF(0x00, 0)

drivers/crypto/rockchip/rk3288_crypto.h

64

#define RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_INPUT _SBF(0x01, 0)

drivers/crypto/rockchip/rk3288_crypto.h

65

#define RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_OUTPUT _SBF(0x02, 0)

drivers/crypto/rockchip/rk3288_crypto.h

86

#define RK_CRYPTO_AES_ECB_MODE _SBF(0x00, 4)

drivers/crypto/rockchip/rk3288_crypto.h

87

#define RK_CRYPTO_AES_CBC_MODE _SBF(0x01, 4)

drivers/crypto/rockchip/rk3288_crypto.h

88

#define RK_CRYPTO_AES_CTR_MODE _SBF(0x02, 4)

drivers/crypto/rockchip/rk3288_crypto.h

89

#define RK_CRYPTO_AES_128BIT_key _SBF(0x00, 2)

drivers/crypto/rockchip/rk3288_crypto.h

90

#define RK_CRYPTO_AES_192BIT_key _SBF(0x01, 2)

drivers/crypto/rockchip/rk3288_crypto.h

91

#define RK_CRYPTO_AES_256BIT_key _SBF(0x02, 2)

drivers/crypto/rockchip/rk3288_crypto_ahash.c

93

RK_CRYPTO_HASH_FLUSH | _SBF(0xffff, 16);

drivers/crypto/rockchip/rk3288_crypto_ahash.c

98

reg_status |= _SBF(0xffff, 16);

drivers/crypto/rockchip/rk3288_crypto_skcipher.c

296

_SBF(RK_CRYPTO_BLOCK_START, 16));

drivers/crypto/s5p-sss.c

123

#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)

drivers/crypto/s5p-sss.c

124

#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)

drivers/crypto/s5p-sss.c

125

#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)

drivers/crypto/s5p-sss.c

127

#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)

drivers/crypto/s5p-sss.c

128

#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)

drivers/crypto/s5p-sss.c

129

#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)

drivers/crypto/s5p-sss.c

153

#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)

drivers/crypto/s5p-sss.c

154

#define FLAGS_AES_CBC _SBF(1, 0x01)

drivers/crypto/s5p-sss.c

155

#define FLAGS_AES_CTR _SBF(1, 0x02)

drivers/crypto/s5p-sss.c

165

#define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00)

drivers/crypto/s5p-sss.c

166

#define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01)

drivers/crypto/s5p-sss.c

167

#define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02)

drivers/crypto/s5p-sss.c

169

#define SSS_HASH_ENGINE_MASK _SBF(1, 0x03)

drivers/crypto/s5p-sss.c

82

#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)

drivers/crypto/s5p-sss.c

83

#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)

drivers/crypto/s5p-sss.c

84

#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)

drivers/crypto/s5p-sss.c

85

#define SSS_HASHIN_MASK _SBF(0, 0x03)

drivers/mmc/host/dw_mmc.h

372

#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))