Symbol: _PIPE
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6139
WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
6143
WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
drivers/gpu/drm/gma500/psb_intel_reg.h
1282
#define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
drivers/gpu/drm/gma500/psb_intel_reg.h
1288
#define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
drivers/gpu/drm/gma500/psb_intel_reg.h
1307
#define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)
drivers/gpu/drm/gma500/psb_intel_reg.h
1311
#define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
drivers/gpu/drm/gma500/psb_intel_reg.h
1481
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
drivers/gpu/drm/gma500/psb_intel_reg.h
1482
#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
drivers/gpu/drm/gma500/psb_intel_reg.h
1483
#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
drivers/gpu/drm/gma500/psb_intel_reg.h
1484
#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
24
(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
drivers/gpu/drm/i915/display/intel_color_regs.h
222
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
drivers/gpu/drm/i915/display/intel_color_regs.h
223
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
drivers/gpu/drm/i915/display/intel_color_regs.h
224
#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */
drivers/gpu/drm/i915/display/intel_color_regs.h
308
#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
drivers/gpu/drm/i915/display/intel_color_regs.h
309
#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
drivers/gpu/drm/i915/display/intel_color_regs.h
48
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
drivers/gpu/drm/i915/display/intel_color_regs.h
65
#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
drivers/gpu/drm/i915/display/intel_color_regs.h
69
#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */
drivers/gpu/drm/i915/display/intel_cursor_regs.h
80
#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
23
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
drivers/gpu/drm/i915/display/intel_display_regs.h
2401
#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
drivers/gpu/drm/i915/display/intel_dmc_regs.h
372
_PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
drivers/gpu/drm/i915/display/intel_dmc_regs.h
373
_PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
drivers/gpu/drm/i915/display/intel_dmc_regs.h
374
_PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
drivers/gpu/drm/i915/display/intel_dmc_regs.h
375
_PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
drivers/gpu/drm/i915/display/intel_sprite_regs.h
109
#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
drivers/gpu/drm/i915/display/intel_sprite_regs.h
113
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
drivers/gpu/drm/i915/display/intel_sprite_regs.h
219
#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
drivers/gpu/drm/i915/display/intel_sprite_regs.h
223
#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
drivers/gpu/drm/i915/display/intel_sprite_regs.h
227
#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
drivers/gpu/drm/i915/display/intel_sprite_regs.h
231
_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
drivers/gpu/drm/i915/display/intel_sprite_regs.h
90
#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
12
_PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
22
_PIPE((pipe), (reg_1_a), (reg_1_b)), \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
23
_PIPE((pipe), (reg_2_a), (reg_2_b)), \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
24
_PIPE((pipe), (reg_5_a), (reg_5_b)), \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
25
_PIPE((pipe), (reg_6_a), (reg_6_b)))
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
295
#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
301
#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
303
#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
312
#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
314
#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
323
#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
325
#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
334
#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
336
#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
345
#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
347
#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
356
#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
358
#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
367
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
369
#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
379
#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
381
#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
390
#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
392
#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
401
#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
403
#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
253
#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
267
#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
275
#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
drivers/gpu/drm/i915/gvt/reg.h
58
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)