drivers/gpu/drm/i915/display/i9xx_plane_regs.h

100

#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

107

#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

93

#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)

drivers/gpu/drm/i915/display/intel_color_regs.h

264

#define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)

drivers/gpu/drm/i915/display/intel_color_regs.h

265

#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)

drivers/gpu/drm/i915/display/intel_color_regs.h

266

#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)

drivers/gpu/drm/i915/display/intel_color_regs.h

267

#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)

drivers/gpu/drm/i915/display/intel_color_regs.h

268

#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)

drivers/gpu/drm/i915/display/intel_color_regs.h

269

#define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)

drivers/gpu/drm/i915/display/intel_display_regs.h

1025

#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1029

#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1033

#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1037

#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1041

#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1045

#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)

drivers/gpu/drm/i915/display/intel_display_regs.h

1049

#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1053

#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)

drivers/gpu/drm/i915/display/intel_display_regs.h

1946

#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

1950

#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1954

#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1958

#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1962

#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1966

#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1971

#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\

drivers/gpu/drm/i915/display/intel_display_regs.h

1976

#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1991

#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

1995

#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

1999

#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)

drivers/gpu/drm/i915/display/intel_display_regs.h

2235

#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2292

#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2306

#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2333

#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

2483

#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)

drivers/gpu/drm/i915/display/intel_display_regs.h

2490

#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)

drivers/gpu/drm/i915/display/intel_display_regs.h

2935

#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

348

#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

356

#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

364

#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

372

#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

380

#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

388

#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

396

#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)

drivers/gpu/drm/i915/display/intel_display_regs.h

404

#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

408

#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

412

#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

973

#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)

drivers/gpu/drm/i915/display/intel_display_regs.h

980

#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

12

#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

63

#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

67

#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

71

#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

75

#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

79

#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

82

#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

85

#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

88

#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)

drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h

91

#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)

drivers/gpu/drm/i915/display/intel_psr_regs.h

100

#define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */

drivers/gpu/drm/i915/display/intel_psr_regs.h

105

#define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

13

#define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

130

#define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

137

#define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

157

#define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

203

#define PSR_EVENT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

223

#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

229

#define _PSR2_SU_STATUS(dev_priv, tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)

drivers/gpu/drm/i915/display/intel_psr_regs.h

237

#define PSR2_MAN_TRK_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

27

#define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

270

#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

280

#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

304

#define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

70

#define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

71

#define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)

drivers/gpu/drm/i915/display/intel_psr_regs.h

90

#define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

105

#define TRANS_VRR_VMIN(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMIN_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

112

#define TRANS_VRR_VMAXSHIFT(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAXSHIFT_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

121

#define TRANS_VRR_STATUS(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

141

#define TRANS_VRR_VTOTAL_PREV(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VTOTAL_PREV_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

151

#define TRANS_VRR_FLIPLINE(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_FLIPLINE_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

158

#define TRANS_VRR_STATUS2(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_STATUS2_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

165

#define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

170

#define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

178

#define EMP_AS_SDP_TL(display, trans) _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

183

#define TRANS_CMRR_M_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

186

#define TRANS_CMRR_M_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_HI_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

189

#define TRANS_CMRR_N_LO(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_LO_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

192

#define TRANS_CMRR_N_HI(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_CMRR_N_HI_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

82

#define TRANS_VRR_CTL(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_CTL_A)

drivers/gpu/drm/i915/display/intel_vrr_regs.h

98

#define TRANS_VRR_VMAX(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VMAX_A)