drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

42

#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)

drivers/gpu/drm/i915/display/icl_dsi_regs.h

106

#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

113

#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

118

#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

144

#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

149

#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

16

#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

171

#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

176

#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

21

#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

38

#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

48

#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

54

#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

90

#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/icl_dsi_regs.h

98

#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

15

#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2305

#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2332

#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2348

#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2446

#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)

drivers/gpu/drm/i915/display/intel_display_regs.h

2695

#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2706

#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_display_regs.h

28

#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \

drivers/gpu/drm/i915/display/intel_display_regs.h

2889

#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)

drivers/gpu/drm/i915/display/intel_dp_aux_regs.h

26

#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \

drivers/gpu/drm/i915/display/intel_dp_aux_regs.h

33

#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)

drivers/gpu/drm/i915/display/intel_dvo_regs.h

14

#define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB)

drivers/gpu/drm/i915/display/intel_dvo_regs.h

48

#define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)

drivers/gpu/drm/i915/display/intel_hdcp_regs.h

258

#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

163

#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

173

#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

191

#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

203

#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

216

#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

227

#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

238

#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

250

#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

268

#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \

drivers/gpu/drm/i915/display/intel_mg_phy_regs.h

278

#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \

drivers/gpu/drm/i915/display/intel_psr_regs.h

319

#define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)

drivers/gpu/drm/i915/display/intel_psr_regs.h

330

#define PORT_ALPM_LFPS_CTL(port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)