drivers/gpu/drm/i915/gt/intel_workarounds.c

326

wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

333

wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

drivers/gpu/drm/i915/i915_perf.c

2638

_MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,

drivers/gpu/drm/i915/i915_perf.c

2850

return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,

drivers/gpu/drm/i915/i915_reg_defs.h

118

#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })

drivers/gpu/drm/i915/i915_reg_defs.h

119

#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))

drivers/gpu/drm/xe/xe_eu_stall.c

507

read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);

drivers/gpu/drm/xe/xe_eu_stall.c

686

read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);

drivers/gpu/drm/xe/xe_eu_stall.c

698

reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,

drivers/gpu/drm/xe/xe_oa.c

1061

return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,

drivers/gpu/drm/xe/xe_oa.c

1068

return _MASKED_FIELD(OAG_OA_DEBUG_BUF_SIZE_SELECT,

drivers/gpu/drm/xe/xe_oa.c

760

_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,

drivers/gpu/drm/xe/xe_oa.c

784

_MASKED_FIELD(CTX_CTRL_OAC_CONTEXT_ENABLE,

drivers/gpu/drm/xe/xe_oa.c

786

_MASKED_FIELD(CTX_CTRL_RUN_ALONE, enable ? CTX_CTRL_RUN_ALONE : 0),

drivers/gpu/drm/xe/xe_oa.c

814

return _MASKED_FIELD(OAG_OA_DEBUG_DISABLE_MMIO_TRG,