_ASM_INSN_IF_MIPS
_ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8)) \
_ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \
_ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \
_ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \
_ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \
_ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \
_ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \
_ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \
_ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \
#ifndef _ASM_INSN_IF_MIPS
_ASM_INSN_IF_MIPS(0x42000004)
_ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) \
_ASM_INSN_IF_MIPS(0x42000010) \
_ASM_INSN_IF_MIPS(0x42000009) \
_ASM_INSN_IF_MIPS(0x4200000a) \
_ASM_INSN_IF_MIPS(0x4200000e) \
_ASM_INSN_IF_MIPS(0x4200000c) \
_ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
_ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
_ASM_INSN_IF_MIPS(0x00000810 | %X1) \
_ASM_INSN_IF_MIPS(0x00200011 | %X1) \
_ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6) \
_ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6) \
_ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \