ZL_REG
#define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1)
#define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1)
#define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1)
#define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1)
#define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1)
#define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1)
#define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1)
#define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1)
#define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1)
#define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1)
#define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1)
#define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2)
#define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2)
#define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1)
#define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2)
#define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2)
#define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2)
#define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2)
#define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1)
#define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6)
#define ZL_REG_REF_PHASE_OFFSET_COMP_32 ZL_REG(10, 0x28, 4)
#define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1)
#define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4)
#define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2)
#define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1)
#define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2)
#define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1)
#define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2)
#define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4)
#define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2)
#define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2)
#define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2)
#define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1)
#define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1)
#define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4)
#define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4)
#define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4)
#define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4)
#define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4)
#define ZL_REG_HWREG_OP ZL_REG(0xff, 0x00, 1)
#define ZL_REG_HWREG_ADDR ZL_REG(0xff, 0x04, 4)
#define ZL_REG_HWREG_WRITE_DATA ZL_REG(0xff, 0x08, 4)
#define ZL_REG_HWREG_READ_DATA ZL_REG(0xff, 0x0c, 4)
#define ZL_REG_FLASH_HASH ZL_REG(0, 0x78, 4)
#define ZL_REG_FLASH_FAMILY ZL_REG(0, 0x7c, 1)
#define ZL_REG_FLASH_RELEASE ZL_REG(0, 0x7d, 1)
#define ZL_REG_HOST_CONTROL ZL_REG(1, 0x02, 1)
#define ZL_REG_IMAGE_START_ADDR ZL_REG(1, 0x04, 4)
#define ZL_REG_IMAGE_SIZE ZL_REG(1, 0x08, 4)
#define ZL_REG_FLASH_INDEX_READ ZL_REG(1, 0x0c, 4)
#define ZL_REG_FLASH_INDEX_WRITE ZL_REG(1, 0x10, 4)
#define ZL_REG_FILL_PATTERN ZL_REG(1, 0x14, 4)
#define ZL_REG_WRITE_FLASH ZL_REG(1, 0x18, 1)
#define ZL_REG_FLASH_INFO ZL_REG(2, 0x00, 1)
#define ZL_REG_ERROR_COUNT ZL_REG(2, 0x04, 4)
#define ZL_REG_ERROR_CAUSE ZL_REG(2, 0x08, 4)
#define ZL_REG_OP_STATE ZL_REG(2, 0x14, 1)
#define ZL_REG_INFO ZL_REG(0, 0x00, 1)
#define ZL_REG_ID ZL_REG(0, 0x01, 2)
#define ZL_REG_REVISION ZL_REG(0, 0x03, 2)
#define ZL_REG_FW_VER ZL_REG(0, 0x05, 2)
#define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4)
#define ZL_REG_RESET_STATUS ZL_REG(0, 0x18, 1)