XE_REG_MCR - Linux

drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

11

#define XEHPC_EUSTALL_BASE XE_REG_MCR(0xe520)

drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

16

#define XEHPC_EUSTALL_BASE_UPPER XE_REG_MCR(0xe524)

drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

18

#define XEHPC_EUSTALL_REPORT XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

22

#define XEHPC_EUSTALL_REPORT1 XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

25

#define XEHPC_EUSTALL_CTRL XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

104

#define GAMSTLB_CTRL XE_REG_MCR(0x477c)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

107

#define GAMSTLB_CTRL2 XE_REG_MCR(0x4788)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

114

#define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

117

#define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

120

#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

123

#define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

126

#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

130

#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

133

#define FF_MODE XE_REG_MCR(0x6210)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

140

#define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

147

#define XEHP_FF_MODE2 XE_REG_MCR(0x6604)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

153

#define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

155

#define CACHE_MODE_1 XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

159

#define XEHP_COMMON_SLICE_CHICKEN1 XE_REG_MCR(0x7010, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

166

#define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

169

#define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

177

#define XEHPG_SC_INSTDONE XE_REG_MCR(0x7100)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

178

#define XEHPG_SC_INSTDONE_EXTRA XE_REG_MCR(0x7104)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

179

#define XEHPG_SC_INSTDONE_EXTRA2 XE_REG_MCR(0x7108)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

182

#define XEHP_COMMON_SLICE_CHICKEN4 XE_REG_MCR(0x7300, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

188

#define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

195

#define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

210

#define SQCNT1 XE_REG_MCR(0x8718)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

216

#define XEHP_SQCM XE_REG_MCR(0x8724)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

219

#define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

223

#define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

228

#define CCCHKNREG1 XE_REG_MCR(0x8828)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

330

#define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

342

#define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

346

#define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

349

#define SSMCGCTL9530 XE_REG_MCR(0x9530)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

352

#define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

403

#define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

408

#define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

425

#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

428

#define LSN_VC_REG2 XE_REG_MCR(0xb0c8)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

440

#define L3SQCREG2 XE_REG_MCR(0xb104)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

445

#define L3SQCREG3 XE_REG_MCR(0xb108)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

448

#define SCRATCH3_LBCF XE_REG_MCR(0xb154)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

451

#define XEHP_L3SQCREG5 XE_REG_MCR(0xb158)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

454

#define XEHP_L3SCQREG7 XE_REG_MCR(0xb188)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

457

#define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

459

#define L2COMPUTESIDECTRL XE_REG_MCR(0xb1c0)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

465

#define XE2LPM_L3SQCREG2 XE_REG_MCR(0xb604)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

467

#define XE2LPM_L3SQCREG3 XE_REG_MCR(0xb608)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

469

#define XE2LPM_SCRATCH3_LBCF XE_REG_MCR(0xb654)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

471

#define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

476

#define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

477

#define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

478

#define COMP_MOD_CTRL XE_REG_MCR(0xcf30)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

479

#define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

481

#define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

485

#define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

492

#define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

500

#define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

503

#define SAMPLER_INSTDONE XE_REG_MCR(0xe160)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

504

#define ROW_INSTDONE XE_REG_MCR(0xe164)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

506

#define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

514

#define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

518

#define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

522

#define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

531

#define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

536

#define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

541

#define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

544

#define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

550

#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

558

#define RT_CTRL XE_REG_MCR(0xe530)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

561

#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

564

#define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

568

#define TDL_CHICKEN XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

573

#define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

580

#define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

593

#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

596

#define SARB_CHICKEN1 XE_REG_MCR(0xe90c)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

68

#define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

89

#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

92

#define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)

drivers/gpu/drm/xe/tests/xe_rtp_test.c

31

#define MCR_REG1 XE_REG_MCR(1)

drivers/gpu/drm/xe/tests/xe_rtp_test.c

32

#define MCR_REG2 XE_REG_MCR(2)

drivers/gpu/drm/xe/tests/xe_rtp_test.c

33

#define MCR_REG3 XE_REG_MCR(3)

drivers/gpu/drm/xe/tests/xe_rtp_test.c

34

#define BAD_MCR_REG4 XE_REG_MCR(4)

drivers/gpu/drm/xe/tests/xe_rtp_test.c

35

#define MCR_REG5 XE_REG_MCR(5)

drivers/gpu/drm/xe/xe_guc_ads.c

715

struct xe_reg_mcr mcr_reg = XE_REG_MCR(reg.addr);

drivers/gpu/drm/xe/xe_guc_capture.c

1585

value = xe_gt_mcr_unicast_read(hwe->gt, XE_REG_MCR(desc.reg.addr),

drivers/gpu/drm/xe/xe_pat.c

354

struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));

drivers/gpu/drm/xe/xe_pat.c

360

xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);

drivers/gpu/drm/xe/xe_pat.c

363

xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), pta_entry->value);

drivers/gpu/drm/xe/xe_pat.c

403

u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

428

u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

458

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

516

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

529

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));

drivers/gpu/drm/xe/xe_pat.c

537

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_ATS));