Y1
FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
ASPEED_PINCTRL_PIN(Y1),
SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI);
SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC);
PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2);
FUNC_GROUP_DECL(NDSR2, Y1);
ASPEED_PINCTRL_PIN(Y1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
FUNC_GROUP_DECL(NCTS2, Y1);
FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
ASPEED_PINCTRL_PIN(Y1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
RL(Y1); \
RU(Y1); \
WL(Y1); \
WU(Y1);
WL(Y1); \
WU(Y1); \
RL(Y1); \
RU(Y1);
WL(Y1); \
WU(Y1); \
RL(Y1); \
RU(Y1);
RL(Y1); \
RU(Y1); \
RL(Y1); \
RU(Y1);
I1(X1); I1(X2); I1(Y1); I1(Y2); I1(Z1); I1(Z2);
L(Y1);
U(Y1);
L(Y1);
U(Y1); // should fail
ML(Y1);
MU(Y1);
ML(Y1);
MU(Y1); // should fail
L(Y1);
U(Y1);
L(Y1);
U(Y1);
L(Y1);
U(Y1); // should fail
L(Y1);
U(Y1);
L(Y1);
U(Y1); // should NOT fail
ML(Y1);
MU(Y1);
ML(Y1);
MU(Y1); // should fail
L(Y1);
U(Y1);
L(Y1);
U(Y1); // should fail
ML(Y1);
MU(Y1);
ML(Y1);
MU(Y1); // should fail