drivers/gpu/drm/xe/instructions/xe_mi_commands.h

35

#define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

37

#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

60

#define MI_LRI_NUM_REGS(x) XE_INSTR_NUM_DW(2 * (x) + 1)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

64

#define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

79

#define MI_LOAD_REGISTER_MEM (__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

83

#define MI_LOAD_REGISTER_REG (__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

87

#define MI_COPY_MEM_MEM (__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

97

#define MI_SEMAPHORE_WAIT_TOKEN (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */

drivers/gpu/drm/xe/xe_ring_ops.c

137

dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

200

dw[i++] = MI_BATCH_BUFFER_START | XE_INSTR_NUM_DW(3);