arch/powerpc/xmon/ppc-opc.c

4791

{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},

arch/powerpc/xmon/ppc-opc.c

4792

{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},

arch/powerpc/xmon/ppc-opc.c

4793

{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},

arch/powerpc/xmon/ppc-opc.c

4872

{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},

arch/powerpc/xmon/ppc-opc.c

4873

{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},

arch/powerpc/xmon/ppc-opc.c

4874

{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},

arch/powerpc/xmon/ppc-opc.c

4959

{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},

arch/powerpc/xmon/ppc-opc.c

4960

{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},

arch/powerpc/xmon/ppc-opc.c

4961

{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},

arch/powerpc/xmon/ppc-opc.c

4998

{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},

arch/powerpc/xmon/ppc-opc.c

4999

{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},

arch/powerpc/xmon/ppc-opc.c

5000

{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},

arch/powerpc/xmon/ppc-opc.c

5047

{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},

arch/powerpc/xmon/ppc-opc.c

5048

{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},

arch/powerpc/xmon/ppc-opc.c

5049

{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},

arch/powerpc/xmon/ppc-opc.c

5130

{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},

arch/powerpc/xmon/ppc-opc.c

5448

{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},