Symbol: XTFPGA_CLKFRQ_VADDR
arch/xtensa/platforms/xtfpga/include/platform/serial.h
16
#define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
arch/xtensa/platforms/xtfpga/setup.c
282
serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
arch/xtensa/platforms/xtfpga/setup.c
292
ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
arch/xtensa/platforms/xtfpga/setup.c
67
ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;