arch/xtensa/kernel/perf_event.c

101

[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1),

arch/xtensa/kernel/perf_event.c

102

[C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8),

arch/xtensa/kernel/perf_event.c

107

[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1),

arch/xtensa/kernel/perf_event.c

108

[C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8),

arch/xtensa/kernel/perf_event.c

68

[PERF_COUNT_HW_CPU_CYCLES] = XTENSA_PMU_MASK(0, 0x1),

arch/xtensa/kernel/perf_event.c

69

[PERF_COUNT_HW_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0xffff),

arch/xtensa/kernel/perf_event.c

70

[PERF_COUNT_HW_CACHE_REFERENCES] = XTENSA_PMU_MASK(10, 0x1),

arch/xtensa/kernel/perf_event.c

71

[PERF_COUNT_HW_CACHE_MISSES] = XTENSA_PMU_MASK(12, 0x1),

arch/xtensa/kernel/perf_event.c

73

[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0x490),

arch/xtensa/kernel/perf_event.c

75

[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XTENSA_PMU_MASK(4, 0x1ff),

arch/xtensa/kernel/perf_event.c

77

[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = XTENSA_PMU_MASK(3, 0x1ff),

arch/xtensa/kernel/perf_event.c

85

[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1),

arch/xtensa/kernel/perf_event.c

86

[C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2),

arch/xtensa/kernel/perf_event.c

89

[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1),

arch/xtensa/kernel/perf_event.c

90

[C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2),

arch/xtensa/kernel/perf_event.c

95

[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1),

arch/xtensa/kernel/perf_event.c

96

[C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2),