XRX
if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
i740outb(par, XRX, DRAM_ROW_BNDRY_1);
i740outb(par, XRX, DRAM_ROW_BNDRY_0);
info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
i740outreg_mask(par, XRX, DISPLAY_CNTL,
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
i740outreg_mask(par, XRX, IO_CTNL,
i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);