XILINX_DMA_REG_DMACR
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,