X2APIC_MSR
svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_W, intercept);
svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W, intercept);
svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W, intercept);
svm_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_W, intercept);
X2APIC_MSR(APIC_TASKPRI),
X2APIC_MSR(APIC_EOI),
X2APIC_MSR(APIC_SELF_IPI),
case X2APIC_MSR(APIC_ID):
case X2APIC_MSR(APIC_LVR):
case X2APIC_MSR(APIC_LDR):
case X2APIC_MSR(APIC_SPIV):
case X2APIC_MSR(APIC_ESR):
case X2APIC_MSR(APIC_LVTCMCI):
case X2APIC_MSR(APIC_ICR):
case X2APIC_MSR(APIC_LVTT):
case X2APIC_MSR(APIC_LVTTHMR):
case X2APIC_MSR(APIC_LVTPC):
case X2APIC_MSR(APIC_LVT0):
case X2APIC_MSR(APIC_LVT1):
case X2APIC_MSR(APIC_LVTERR):
case X2APIC_MSR(APIC_TMICT):
case X2APIC_MSR(APIC_TMCCT):
case X2APIC_MSR(APIC_TDCR):
vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW);